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UPSTREAM: drivers/fsp1_1: decouple VBT from execution of GOP driver
Commit2e7f6cc
introduced the 'no graphics init' option for FSP 1.1 SoCs using a GOP driver to init the display, but selecting that option while including a VBT breaks compilation for Braswell and Skylake devices because the VBT and GOP driver are intertwined. This patch decouples the VBT from the GOP driver execution, allowing the 'no graphics init' option to compile (and work) properly when CONFIG_ADD_VBT_DATA_FILE=y. BUG=none BRANCH=none TEST=none Change-Id: I25447b151e00c2505e7c6eff9411adbbadaa9848 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id:660de34bbf
Original-Change-Id: Ifbcf32805177c290c4781b32bbcca679bcb0c297 Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Original-Reviewed-on: https://review.coreboot.org/20210 Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/538572 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
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3 changed files with 40 additions and 40 deletions
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@ -38,7 +38,7 @@ ramstage-y += fsp_util.c
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ramstage-y += hob.c
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ramstage-y += ramstage.c
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ramstage-y += stage_cache.c
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ramstage-$(CONFIG_RUN_FSP_GOP) += vbt.c
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ramstage-$(CONFIG_ADD_VBT_DATA_FILE) += vbt.c
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ramstage-$(CONFIG_MMA) += mma_core.c
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CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
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@ -14,49 +14,10 @@
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*/
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#include <boot/coreboot_tables.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <lib.h>
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/* Reading VBT table from flash */
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const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len)
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{
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size_t vbt_size;
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union {
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const optionrom_vbt_t *data;
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uint32_t *signature;
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} vbt;
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/* Locate the vbt file in cbfs */
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vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, &vbt_size);
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if (!vbt.data) {
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printk(BIOS_INFO,
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"FSP_INFO: VBT data file (vbt.bin) not found in CBFS");
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return NULL;
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}
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/* Validate the vbt file */
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if (*vbt.signature != VBT_SIGNATURE) {
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printk(BIOS_WARNING,
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"FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n");
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return NULL;
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}
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*vbt_len = vbt_size;
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printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n",
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vbt.data, *vbt_len);
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#if IS_ENABLED(CONFIG_DISPLAY_VBT)
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/* Display the vbt file contents */
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printk(BIOS_DEBUG, "VBT Data:\n");
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hexdump(vbt.data, *vbt_len);
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printk(BIOS_DEBUG, "\n");
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#endif
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/* Return the pointer to the vbt file data */
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return vbt.data;
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}
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int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
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{
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VOID *hob_list_ptr;
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@ -15,10 +15,49 @@
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*/
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#include <bootmode.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <fsp/ramstage.h>
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#include <fsp/util.h>
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/* Reading VBT table from flash */
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const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len)
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{
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size_t vbt_size;
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union {
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const optionrom_vbt_t *data;
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uint32_t *signature;
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} vbt;
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/* Locate the vbt file in cbfs */
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vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, &vbt_size);
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if (!vbt.data) {
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printk(BIOS_INFO,
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"FSP_INFO: VBT data file (vbt.bin) not found in CBFS");
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return NULL;
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}
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/* Validate the vbt file */
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if (*vbt.signature != VBT_SIGNATURE) {
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printk(BIOS_WARNING,
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"FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n");
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return NULL;
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}
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*vbt_len = vbt_size;
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printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n",
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vbt.data, *vbt_len);
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#if IS_ENABLED(CONFIG_DISPLAY_VBT)
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/* Display the vbt file contents */
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printk(BIOS_DEBUG, "VBT Data:\n");
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hexdump(vbt.data, *vbt_len);
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printk(BIOS_DEBUG, "\n");
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#endif
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/* Return the pointer to the vbt file data */
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return vbt.data;
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}
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/* Locate VBT and pass it to FSP GOP */
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void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
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{
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