Commit graph

19606 commits

Author SHA1 Message Date
Furquan Shaikh
458efe0fe3 UPSTREAM: soc/intel/apollolake: Use the new SPI driver interface
1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash controller
in different files.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully for reef.

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17562
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793
Reviewed-on: https://chromium-review.googlesource.com/418364
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:33 -08:00
Furquan Shaikh
3729181da3 UPSTREAM: spi: Clean up SPI driver interface
1. Add new structure spi_ctrlr_buses that allows platform to define a
mapping from SPI controller to buses managed by the controller.
2. Provide weak implementations of spi_init and spi_setup_slave that
will be used by platforms using the new interface.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17561
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia6f47941b786299f4d823895898ffb1b36e02f73
Reviewed-on: https://chromium-review.googlesource.com/418363
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:31 -08:00
Furquan Shaikh
3aeec7a66a UPSTREAM: soc/intel/skylake: Remove unwanted spi_release call
Skylake uses a special SPI Flash controller and does not require
spi_claim_bus and spi_release_bus functionality. This was a leftover
call from earlier cleanup, so remove it.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17729
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iea260813cf72b94b7e7c661dbe494a74351dc357
Reviewed-on: https://chromium-review.googlesource.com/418362
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:29 -08:00
Subrata Banik
28eeeb507e UPSTREAM: soc/intel/skylake: Remove redundant BootLoaderTolumSize assignment
BootLoaderTolumSize FSP-M UPD is already initialized with cbmem_overhead_size()
inside driver/fsp2_0/memory_init.c, hence remove the duplicate assignment.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17721
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I0b1d9769cd2a863bf0547ce5f44928cacc5a63b6
Reviewed-on: https://chromium-review.googlesource.com/418361
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:27 -08:00
Paul Menzel
65b1a2f838 UPSTREAM: lib: Add time stamp when starting to finalize chips
Add the new time stamps *finalize chips* to track, when the method
`dev_finalize_chips()` is called, so that the real time of
`write_tables()` is known.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I65ca0ec4c07c2eaa14982989cb206d23d8a2293f
Reviewed-on: https://chromium-review.googlesource.com/418360
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:24 -08:00
Nico Huber
47683793dd UPSTREAM: sio/ite/it8783ef: New super i/o chip
This will be used by new Roda boards. Four UARTs and PS/2 keyboard and
mouse are exposed to ACPI. Since our boards only use the environment
controller part, most of the usual pnp interfaces are untested.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17287
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464
Reviewed-on: https://chromium-review.googlesource.com/418359
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:22 -08:00
Nico Huber
13da02e944 UPSTREAM: sio/acpi: Add more magic bytes to ENTER/EXIT_CONFIG_MODE
ITE super-i/o chips need a fourth byte and have a special register
to exit config mode.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de
Reviewed-on: https://chromium-review.googlesource.com/418358
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:20 -08:00
Nico Huber
c1cc9634eb UPSTREAM: sio/ite/common: Export pnp_enter/exit_conf_state()
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17285
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I8cbfe49516e685c1b3e150b23f9fcac513f1f3dc
Reviewed-on: https://chromium-review.googlesource.com/418357
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 22:46:17 -08:00
Furquan Shaikh
6bb709e552 UPSTREAM: soc/mediatek/mt8173: Do not initialize static variables to 0
CQ-DEPEND=CL:417080,CL:417081,CL:417087
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17765
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ibf0bd772bfdb3bbf6482a0ec9ff90a5c0a8945d2
Reviewed-on: https://chromium-review.googlesource.com/417958
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:51 -08:00
Kyösti Mälkki
b1c81b71d3 UPSTREAM: AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain
Device is of type CPU_CLUSTER, while pci_dev_set_resources()
expects PCI_DOMAIN.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17697
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ib1add47d71071abb6e9c28e3a85dd0b671741b71
Reviewed-on: https://chromium-review.googlesource.com/417957
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:49 -08:00
Kyösti Mälkki
6b899221d7 UPSTREAM: MMCONF_SUPPORT: Drop redundant logging
Resource is actually stored even before read_resources, but
that's where we currently log this resource.

For Intel, use PCI config register offset as the resource
index, while AMD side uses MSR address.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17696
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781
Reviewed-on: https://chromium-review.googlesource.com/417956
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:46 -08:00
Kyösti Mälkki
551e3ef5f5 UPSTREAM: MMCONF_SUPPORT: Consolidate resource registration
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17695
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f
Reviewed-on: https://chromium-review.googlesource.com/417955
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:44 -08:00
Kyösti Mälkki
50f4e327bb UPSTREAM: MMCONF_SUPPORT: Flip default to enabled
Also remove separate MMCONF_SUPPORT_DEFAULT flag.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17694
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0
Reviewed-on: https://chromium-review.googlesource.com/417954
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:41 -08:00
Kyösti Mälkki
ca34ec3605 UPSTREAM: PCI ops: MMCONF_SUPPORT_DEFAULT is required
Doing PCI config operations via MMIO window by default is a
requirement, if supported by the platform. This means chipset
or CPU code must enable MMCONF operations early in bootblock
already, or before platform-specific romstage entry.

Platforms are allowed to have NO_MMCONF_SUPPORT only in the
case it is actually not implemented in the silicon.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d
Reviewed-on: https://chromium-review.googlesource.com/417953
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:39 -08:00
Aaron Durbin
63751265ea UPSTREAM: mainboard/google/reef: adjust chromeos.fmd regions
- Drastically reduced RW_MRC_CACHE size to hold one update. Now
  that this area isn't changing after every S5 entry there's no
  need make it so large.
- ELOG area reduced by 4KiB for subsequent area alignment. In practice
  this doesn't matter because the elog library only uses 4KiB bytes.
  16KiB->12KiB is a nop.
- Moved RW_NVRAM for subsequent alignment.
- Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries
  and sized to 64KiB multiples. This ensures updates don't need a
  read-modify-write that could force a system into recovery if
  an inopportune power event occurred.

BUG=chrome-os-partner:60492
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17727
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540
Reviewed-on: https://chromium-review.googlesource.com/417952
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:36 -08:00
Nico Huber
d3434e7964 UPSTREAM: buildgcc: Be less restrictive when trying to build GNAT
It turned out that newer GNAT versions can build our current (5.3.0)
GNAT without bootstrapping. So adapt the version enforcement.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Ie7189e8bcadeee56cf5c2172e8c0ae7cd534685a
Reviewed-on: https://chromium-review.googlesource.com/417951
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:34 -08:00
Nico Huber
effdc84b1f UPSTREAM: buildgcc: Fix function prototype in GCC
With some newer versions of GCC (experienced with GCC 6.2.1 on Arch-
Linux) the first stage of a boostrapping fails due to a mismatching
function prototype. Also add a missing `static` to the signature.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Ia927036ccd725550f1191890515578bc80c74f80
Reviewed-on: https://chromium-review.googlesource.com/417950
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:31 -08:00
Kyösti Mälkki
0b8df7e358 UPSTREAM: cpu/amd/mtrr.h: Drop excessive includes
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17736
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf
Reviewed-on: https://chromium-review.googlesource.com/417949
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:29 -08:00
Kyösti Mälkki
685e18945a UPSTREAM: cpu/x86/msr.h: Drop excessive includes
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17735
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903
Reviewed-on: https://chromium-review.googlesource.com/417948
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:26 -08:00
Kyösti Mälkki
b160f80489 UPSTREAM: cpu/cpu.h: Drop excessive includes
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17734
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607
Reviewed-on: https://chromium-review.googlesource.com/417947
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:24 -08:00
Kyösti Mälkki
15a16b97cc UPSTREAM: CPU: Declare cpu_phys_address_size() for all arch
Resource allocator and 64-bit PCI BARs will need it and
PCI use is not really restricted to x86.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17733
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532
Reviewed-on: https://chromium-review.googlesource.com/417946
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:22 -08:00
Kyösti Mälkki
bcfc212c21 UPSTREAM: CPU: Move SMM prototypes under x86
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17732
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6
Reviewed-on: https://chromium-review.googlesource.com/417945
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:19 -08:00
Kyösti Mälkki
ef59bb700e UPSTREAM: PCI ops: Remove pci_mmio_xx() in ramstage
MMCONF operations are already the default so these
would never be used.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17691
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I671f3d2847742e400bc4ecfccc088e3b79d43070
Reviewed-on: https://chromium-review.googlesource.com/417944
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:17 -08:00
Kyösti Mälkki
8701c3dfbf UPSTREAM: PCI ops: Rename pcie_xx() to pci_mmio_xx()
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17530
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37
Reviewed-on: https://chromium-review.googlesource.com/417943
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:14 -08:00
Kyösti Mälkki
44ece8eb25 UPSTREAM: PCI ops: Define read-modify-write routines globally
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17690
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd
Reviewed-on: https://chromium-review.googlesource.com/417942
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:12 -08:00
Kyösti Mälkki
24724235d7 UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

I liked the style of code in pci_mmio_cfg.h more, and used those to
replace the ones in io.h.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17689
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92
Reviewed-on: https://chromium-review.googlesource.com/417941
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:10 -08:00
Kyösti Mälkki
38db8a0a5f UPSTREAM: PCI ops: Remove conflicting duplicate declarations
The code originates from times before __SIMPLE_DEVICE__ was
introduced. To keep behaviour unchanged, use explicit PCI
IO operations here.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17720
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f
Reviewed-on: https://chromium-review.googlesource.com/417940
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:07 -08:00
Kyösti Mälkki
c23ee7bbe2 UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17545
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1
Reviewed-on: https://chromium-review.googlesource.com/417078
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:05 -08:00
Kyösti Mälkki
d95ea59eff UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17529
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
Reviewed-on: https://chromium-review.googlesource.com/417077
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:02 -08:00
Jonathan Neuschäfer
49cc425e52 UPSTREAM: mb/lowrisc/nexys4ddr: Read RAM information from the config string
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17710
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I9147eca0b536b6267d58f6e8baa37b6950b35160
Reviewed-on: https://chromium-review.googlesource.com/417076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:31:00 -08:00
Jonathan Neuschäfer
2c7f52e8a0 UPSTREAM: mb/lowrisc/nexys4ddr: Initialize CBMEM in romstage
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17707
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ic1706ae8ab3cbef8f445d70cb78fa9d3301d87be
Reviewed-on: https://chromium-review.googlesource.com/417075
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:58 -08:00
Jonathan Neuschäfer
2421dffc74 UPSTREAM: soc/lowrisc: Place CBMEM at top of autodetected RAM
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17708
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I9f169db330d1792128db7a6308ed3afbe5803c03
Reviewed-on: https://chromium-review.googlesource.com/417074
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:55 -08:00
Jonathan Neuschäfer
73a36696f0 UPSTREAM: soc/marvell/mvmap2315: Fix integer arithmetic
Replace logical with bitwise AND operator.

BUG=None
BRANCH=None
TEST=None

Reported-by: Coverity (CID 1362808)
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17401
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I712fab61fbbc833fc2b2575948a875e2f07fd5de
Reviewed-on: https://chromium-review.googlesource.com/417073
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:53 -08:00
Jonathan Neuschäfer
da29c1c530 UPSTREAM: riscv: Stub out sbi_(un)mask_interrupt
Linux needs these SBI calls, but so far it seems to work when they don't
do anything.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17593
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I2cd0bb3ab91e89805fed84ec87e4a48ce70c3a46
Reviewed-on: https://chromium-review.googlesource.com/417072
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:51 -08:00
Jonathan Neuschäfer
b3f01e9331 UPSTREAM: soc/ucb/riscv: Place CBMEM at top of autodetected RAM
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17595
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ida016aec11ccdb8da8d2ae1d30ddca16b069be11
Reviewed-on: https://chromium-review.googlesource.com/417071
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:48 -08:00
Jonathan Neuschäfer
9a26711c29 UPSTREAM: arch/riscv/mcall.c: Return the correct memory base and size
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17594
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ibf471787ccb4f5393b0af737a9f7fc47b853a41a
Reviewed-on: https://chromium-review.googlesource.com/417070
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:46 -08:00
Werner Zeh
b105b076be UPSTREAM: mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missing
Do not abort the initialization of PTN3460 if HW-ID could not be
retrieved and just assume that the HW-ID does not match 7.9.2.0.
In this case PTN3460 will be setup to a working condition even
if this field is missing.
This makes this driver more robust with faulty blocks.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17671
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

Change-Id: I301fb165a7924768e44182d92be820294beb0280
Reviewed-on: https://chromium-review.googlesource.com/417092
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:44 -08:00
Werner Zeh
1a7b17c54f UPSTREAM: vendorcode/siemens: Ensure a given info block is available for a field
While searching for a field in all blocks ensure that the checked block
is available and can be used. In this way a field can be retrieved from
every block and not just the first one.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17670
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

Change-Id: Idbd7656ab0664763cb065f5e817193ad1d9e0871
Reviewed-on: https://chromium-review.googlesource.com/417091
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:42 -08:00
Kyösti Mälkki
5a7e617031 UPSTREAM: AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set
It gets selected from CPU_AMD_MODEL10XXX.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17692
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iffab43edc1152b07ba2af6273d4b5eb94afe33ba
Reviewed-on: https://chromium-review.googlesource.com/417090
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:39 -08:00
Kyösti Mälkki
3faa7ad49f UPSTREAM: intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULT
Untested.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17544
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I61ab1e5279c995f933971332673aa4ca0150e80c
Reviewed-on: https://chromium-review.googlesource.com/417089
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:37 -08:00
Kyösti Mälkki
7f941707b2 UPSTREAM: intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULT
Boards with this chipset do not have any reference of
MMCONF_BASE_ADDRESS being written to chipset registers.
Either board support is already broken or FSP takes
care of this early and Kconfig lacks the notice that
this parameter must match with the chosen FSP binary.

CPU bootblock associated with this chipset uses
exclusive PCI IO access already.

Untested.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17547
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08
Reviewed-on: https://chromium-review.googlesource.com/417088
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:34 -08:00
Furquan Shaikh
8613ba7028 UPSTREAM: spi_flash: Make a deep copy of spi_slave structure
Commit 36b81af (spi: Pass pointer to spi_slave structure in
spi_setup_slave) changes the way spi_setup_slave handles the spi_slave
structure. Instead of expecting spi controller drivers to maintain
spi_slave structure in CAR_GLOBAL/data section, caller is expected to
manage the spi_slave structure. This requires that spi_flash drivers
maintain spi_slave structure and flash probe function needs to make a
copy of the passed in spi_slave structure.

This change fixes the regression on Lenovo X230 and other mainboards.

CQ-DEPEND=CL:417081,CL:417080,CL:417958
BUG=chrome-os-partner:59832
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17728
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>

Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab
Reviewed-on: https://chromium-review.googlesource.com/417087
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:32 -08:00
Martin Roth
e9f1726b3d UPSTREAM: mainboard & southbridge: Clear files that are just headers
These headers & comments indicating a lack of functionality don't help
anything.  We discourage copyrights and licenses on empty files, so
just clear these.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17657
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d
Reviewed-on: https://chromium-review.googlesource.com/417086
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:28 -08:00
Matt DeVillier
52015bf519 UPSTREAM: Add/Combine Haswell Chromebooks using variant board scheme
Combine existing boards google/falco and google/peppy with new
ChromeOS devices leon and wolf, using their common reference board
(slippy) as a base.

Chromium sources used:
firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...]
firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode]
firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...]

Additionally, some minor cleanup/changes were made:
- I2C devices set to use ACPI (vs PCI) mode
- I2C device ACPI entries adjusted as per above
- I2C devices set to use level (vs edge) interrupt triggering
- XHCI finalization enabled in devicetree
- HDA verb entries use simplified macro entry format

Existing google/falco and google/peppy boards will be removed in a
subsequent commit.

Variant setup modeled after google/beltino

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17621
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be
Reviewed-on: https://chromium-review.googlesource.com/417085
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:25 -08:00
Matt DeVillier
1b9f96c8c1 UPSTREAM: Remove boards google/falco and google/peppy
No need for these boards to exist separately once included as
variants under google/slippy

CQ-DEPEND=CL:417880
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17622
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I52a476ceaadf50487d6fe21e796d7844f946d8b3
Reviewed-on: https://chromium-review.googlesource.com/417084
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:23 -08:00
Martin Roth
ddf8db1ab5 UPSTREAM: rockchip/rk3399: display: Update edp initialization retry
Follow on patch to clean up the previous retry code.
Previous patches:
coreboot commit 079b5c65
(rockchip/rk3399: display: Retry edp initialization if it fails)
cros commit 28c57a6e
(rockchip/rk3399: display: retry edp initialization if edp initial fail)

- Reduce the jumping around via goto statements
- Break the retry code out into a separate function that also
prints the error messages.

BRANCH=gru
BUG=chrome-os-partner:60150
TEST=Rebuild Kevin and Gru

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17642
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>

Change-Id: I3b6cf572073e4dcac83da09621bafde179af2613
Reviewed-on: https://chromium-review.googlesource.com/417083
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:20 -08:00
Patrick Rudolph
0dea366908 UPSTREAM: nb/intel/sandybridge/raminit: Split raminit.c
Split raminit.c into smaller parts. Move all functions that will
be used by chip-specific code into raminit_common.c.
The chip-specific changes includes new configuration values
for IvyBridge and 100Mhz reference clock support, including new
frequencies.

No functionality is changed.

Tested on Lenovo T420.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17604
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: If7bb5949f4b771430f3dba1b754ad241a7e8426b
Reviewed-on: https://chromium-review.googlesource.com/417082
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:18 -08:00
Furquan Shaikh
9a2bc7d727 UPSTREAM: spi: Define and use spi_ctrlr structure
1. Define a new structure spi_ctrlr that allows platforms to define
callbacks for spi operations (claim bus, release bus, transfer).
2. Add a new member (pointer to spi_ctrlr structure) in spi_slave
structure which will be initialized by call to spi_setup_slave.
3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c
which will make appropriate calls to ctrlr functions.

CQ-DEPEND=CL:417080,CL:417087,CL:417958
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17684
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e
Reviewed-on: https://chromium-review.googlesource.com/417081
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:16 -08:00
Furquan Shaikh
737d4e09fe UPSTREAM: spi: Pass pointer to spi_slave structure in spi_setup_slave
For spi_setup_slave, instead of making the platform driver return a
pointer to spi_slave structure, pass in a structure pointer that can be
filled in by the driver as required. This removes the need for platform
drivers to maintain a slave structure in data/CAR section.

CQ-DEPEND=CL:417081,CL:417087,CL:417958
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17683
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573
Reviewed-on: https://chromium-review.googlesource.com/417080
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08 12:30:13 -08:00
Furquan Shaikh
15797fb67c UPSTREAM: spi: Fix parameter types for spi functions
1. Use size_t instead of unsigned int for bytes_out and bytes_in.
2. Use const attribute for spi_slave structure passed into xfer, claim
bus and release bus functions.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17682
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a
Reviewed-on: https://chromium-review.googlesource.com/417079
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 00:36:50 -08:00