Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: soc/lowrisc: Place CBMEM at top of autodetected RAM

Browse source 
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17708
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I9f169db330d1792128db7a6308ed3afbe5803c03
Reviewed-on: https://chromium-review.googlesource.com/417074
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Jonathan Neuschäfer 2016-11-24 08:26:03 +01:00 • committed by chrome-bot
parent 73a36696f0
commit 2421dffc74
1 changed files with 7 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/soc/lowrisc/lowrisc/cbmem.c
View file

@ -11,13 +11,15 @@
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <cbmem.h>
#include <commonlib/configstring.h>
void *cbmem_top(void)
{
// TODO: find out how the lowrisc SOC decides to provide
// this information, when they know.
printk(BIOS_SPEW, "Returning hard-coded 128M; fix me\n");
return (void *)((uintptr_t)(2ULL*GiB+128*MiB));
uintptr_t base;
size_t size;
query_mem(configstring(), &base, &size);
return (void *)(base + size);
}