Variable name shadows parameter name used on other functions,
and it can be local anyway after function removal.
Change-Id: I3164b15b33d877fef139f48ab2091e60e3124c3b
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15240
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
(cherry-picked from commit 072d436b3f)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354201
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Not masking any bits in Operating System Capabilities, which means we
support all the capabilities that OS passed in Arg3
Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15021
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit f2a50d1231)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354200
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of programming unsupported CAS use the highest supported
value. Start at DDR3 maximum of CAS 18T.
Increase error message verbosity level.
Useful for overclocking.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Allows to run a DDR3-1600 DIMM at 933Mhz.
Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/15217
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
(cherry-picked from commit 55409ebbb6)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354199
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Calculate the value from current DDR frequency.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/15184
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
(cherry-picked from commit d4c53e3fdd)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354198
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add Ramaxel DRAM manufacturer id.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
The manufacturer name shows up in dmidecode.
Change-Id: I14cdc82c09f0f990e2ba18083748d11d79e53874
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/15183
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit 4307835d26)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354197
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Set max_mem_clock_mhz in devicetree to 933Mhz.
Allows to run the memory at up to DDR3-1866.
The same frequency was allowed within the first vendor bios,
but Lenovo than decided to limit it to DDR3-1333.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
The RAM is now running at DDR3-1600 instead of DDR3-1333.
This gives about 4% performance increase in glmark2 using the
Intel GPU.
Change-Id: If15be497402d84a2778f0434b6381a64eda832d6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/15158
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 7bddd30e94)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354194
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
CPU_MICROCODE_MULTIPLE_FILES relies on SUPPORT_CPU_MICROCODE_CBFS,
which is not set if CPU_MICROCODE_CBFS_NONE is set.
This makes selecting CPU_MICROCODE_MULTIPLE_FILES conditional.
Change-Id: I0c28f99a1b868bbf90a6f048cce3bea4ff849f76
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/15259
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
(cherry-picked from commit 4089a17cb9)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354193
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.
Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15238
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit d71cfd2041)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354191
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Required EHCI state is maintained as a CAR_GLOBAL to have it
properly migrated.
Change-Id: I8df413bec6faae4952670710c8ac804e0331c966
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15236
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry-picked from commit 4b86314495)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354190
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Implement function that automatically converts a SELF payload,
extracted from the CBFS, into an ELF file.
The code has been tested on the following payloads:
Working: GRUB, FILO, SeaBIOS, nvramcui, coreinfo and tint
Currently not working: none
CQ-DEPEND=CL:354166
BUG=None
BRANCH=None
TEST=None
Change-Id: I51599e65419bfa4ada8fe24b119acb20c9936227
Original-Signed-off-by: Antonello Dettori <dettori.an@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15139
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354171
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Allow to write multiple phdrs, one for each non-consecutive section
of the ELF.
Previously it only worked for ELFs contaning a single
program header.
BUG=None
BRANCH=None
TEST=None
Change-Id: If6f95e999373a0cab4414b811e8ced4c93c67c30
Original-Signed-off-by: Antonello Dettori <dev@dettori.io>
Original-Reviewed-on: https://review.coreboot.org/15215
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354170
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
We want to be able to easily change SDRAM clock rate for debugging
purposes. This patch adds configurations for 4 different clock rates.
Same configs are used for all rk3399 boards at 200, 666 and 800 MHz.
Kevin board does not run reliably at 666 MHz, an option for it is
added to run at 300 MHz, this option is available to Kevin only.
There is not much room left in the coreboot romstage section, this is
why the config file for 928 MHz is being added with this patch but is
not included in the code, one of the lower frequency options will have
to be dropped for the higher frequency option to be added.
BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 3600" and pass on both kevin and
gru. Verified that on Kevin the firmware reports starting up
SDRAM at 300 MHz and on Gru - at 800 MHz.
Change-Id: I08bccd40147ad89d851b995a8aab4d2b6da8258a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353493
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
This is a purely cosmetic change replacing some of the more prominent
copy and paste sections of the code with compressed versions of the
same.
BRANCH=none
BUG=none
TEST=with the rest of the patches applied stressapptest still runs for
an hour on both Kevin and Gru.
Change-Id: I362e0e261209ae4d4890ecb0e08bb1956c172ffd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353774
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
for per cs training, there should be more cycles to switch delay line.
so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5.
BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass
Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/352953
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Add code to start up elog. This uses the EC RTC to obtain the timestamp.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages
Change-Id: I0fcf55b3feccf9a0ad915deb6d323b65bf2e9811
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353822
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Add this function and make it return 0, as there is no physical dev switch
(at least I think this is what we are supposed to do).
This is needed for elog to work, which is needed so we can test RTC
properly.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages:
elog_init()
SF: Detected W25Q64 with sector size 0x1000, total 0x800000
elog_find_flash()
FMAP: area RW_ELOG found @ 5d8000 (32768 bytes)
elog_scan_flash()
elog_is_buffer_clear(base=0x000000000031d668 size=4096)
ELOG: flash area invalid
elog_flash_erase(address=0x000000000031d668 offset=0x005d8000 size=4096)
SF: Successfully erased 4096 bytes @ 0x5d8000
elog_prepare_empty()
elog_flash_write(address=0x000000000031d668 offset=0x005d8000 size=8)
elog_scan_flash()
elog_is_buffer_clear(base=0x000000000031d668 size=4096)
elog_is_header_valid()
elog_update_event_buffer_state()
elog_is_buffer_clear(base=0x000000000031d670 size=4088)
elog_is_area_valid()
ELOG: FLASH @0x000000000031d668 [SPI 0x005d8000]
ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024
elog_add_event_raw(type=16)
out: cmd=0x44: 03 b9 44 00 00 00 00 00
in-header: 03 3f 00 00 04 00 00 00
in-data: 6e 4c 00 00
elog_flash_write(address=0x000000000031d670 offset=0x005d8008 size=11)
ELOG: Event(16) added with size 11
elog_add_event_raw(type=17)
out: cmd=0x44: 03 b9 44 00 00 00 00 00
in-header: 03 3f 00 00 04 00 00 00
in-data: 6e 4c 00 00
elog_flash_write(address=0x000000000031d67b offset=0x005d8013 size=13)
ELOG: Event(17) added with size 13
elog_add_event_raw(type=A0)
out: cmd=0x44: 03 b9 44 00 00 00 00 00
in-header: 03 3f 00 00 04 00 00 00
in-data: 6e 4c 00 00
elog_flash_write(address=0x000000000031d688 offset=0x005d8020 size=9)
ELOG: Event(A0) added with size 9
elog_add_boot_reason: Logged dev mode boot
I can't actually see the timestamp, but the EC traffic is visible.
Change-Id: I1489c6b874cc49495635aec0bf303f7098455716
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353821
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Display the current time from the EC.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) boot on gru and see output:
Date: 1970-01-17 (Saturday) Time: 1:42:44
Then reboot ~10 seconds later and see output:
Date: 1970-01-17 (Saturday) Time: 1:42:53
Change-Id: I04a072c788ba3fc915e6d73703f966955bbd3e7e
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351783
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Obtain the real-time clock value from the EC on start-up and show the
current time.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits and EC clock set, boot on gru into
Linux shell and check the firmware log:
localhost ~ # grep Date: /sys/firmware/log
Date: 2016-06-20 (Monday) Time: 18:09:16
Change-Id: Iff43b16a86d9fee483420ee2eff5ff3d276716a3
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351781
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Some platforms have an RTC provided by the Chrome OS EC. Allow the EC to
implement rtc_get() so that this can be plumbed in.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits, boot on gru and see output:
Date: 1970-01-17 (Saturday) Time: 1:42:44
Then reboot ~10 seconds later and see output:
Date: 1970-01-17 (Saturday) Time: 1:42:53
Change-Id: Icaa381d32517dfed8d3b7927495b67a027d5ceea
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351780
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Add functions to convert between seconds and a struct rtc_time. Also
add a function that can display the time on the console.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits and after setting RTC on the EC:
boot on gru into linux shell, check firmware log:
localhost ~ # grep Date: /sys/firmware/log
Date: 2016-06-20 (Monday) Time: 18:01:44
Then reboot ~10 seconds and check again:
localhost ~ # grep Date: /sys/firmware/log
Date: 2016-06-20 (Monday) Time: 18:01:54
Change-Id: I344c385e2e4cb995d3a374025c205f01c38b660d
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351782
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reference to CACHE_AS_RAM was from the days we had
romcc boards using socket_mPGA605.
Change-Id: If397db83a01adeda4dd18d8b4c6e89bf0984264a
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15224
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit 831a7ef541)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354185
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This is more of ACPI S3 resume and x86 definition than CBMEM.
Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15190
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry-picked from commit a969ed34db)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354182
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This Kconfig is deprecated, new platforms need to locate
ramstage stack in CBMEM instead.
Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15189
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry-picked from commit bec853e9ad)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354180
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
After write leveling for all ranks, check the
PHY_CLK_WRDQS_SLAVE_DELAY result, if the two ranks in one slice both
meet (0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20) or
(0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0), enable PHY_WRLVL_EARLY_FORCE_ZERO
for this slice, and trigger write leveling again.
BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass
Change-Id: Ic0d7c59404e870a7108ed64bbf3215fcc2d0973e
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351825
To fully define TPM attachment to a SPI interface both bus and CS
(chip select) settings are required. Add the missing CS configuration
option.
BRANCH=none
BUG=chrome-os-partner:50645
TEST=with the rest of the patches applied it is possible to compile in
and run TPM2 SPI driver.
Change-Id: If297df8e5b9526f156ed1414eb9db317d6af5b33
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353913
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This introduces a SPI TPM driver compliant with the TCG issued "TPM
Profile (PTP) Specification Revision 00.43" which can be found by
googling its title.
The driver implements both the hardware flow control protocol and the
TPM state machine.
The hardware flow control allows to map SPI based TPM devices to the
LPC address space on x86 platforms, on all other platforms it needs to
be implemented in the driver software.
The tis layer is somewhat superficial, it might have to be expanded
later.
A lot more implementation details can be found in the code comments.
Also, it is worth mentioning that this is not a complete version of
the driver: its robustness needs to be improved, delay loops need to
be bound, error conditions need to propagate up the call stack.
BRANCH=none
BUG=chrome-os-partner:52132, chrome-os-partner:50645, chrome-os-partner:54141
TEST=with the rest of the patches applied coreboot is able complete
Chrome OS factory initialization of the TPM2 device.
Change-Id: I17d732e66bd231c2289ec289994dd819c6276855
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350124
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The CENTER LOGIC should always be 0.9v and can not be adjust,
so use duty_ns = 2860 to correct CENTER LOGIC to 0.9v. And now
DDR seem run stable on 800MHz on gru board.
BRANCH=none
BUG=chrome-os-partner:54144, chrome-os-partner:53208
TEST=run "stressapptest -M 1024 -s 1000" and pass
Change-Id: I2238da6c17908d09bc284b321d796901317ed9ef
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352772
Checksum is calculated by using 2s complement method. 8-bit sum of the
entire subpart directory from first byte of header to last byte of last
partition directory entry.
BUG=chrome-os-partner:53508
Change-Id: I991d79dfdb5331ab732bf0d71cf8223d63426fa8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15200
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353155
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to
upstream, using google/guado as a baseline.
original source:
branch firmware-rikku-6301.110.B
commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F]
TEST=built and booted Linux on rikku with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.bin)
external reference code (refcode.elf)
Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12802
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/353174
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up the pins and initialize the driver.
BRANCH=none
BUG=chrome-os-partner:50645, chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
communicate with the cr50.
Change-Id: I0ccd8777288e35870658268813c9202dd850c70d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349852
Reviewed-by: Douglas Anderson <dianders@chromium.org>
This register is described in the TRM in section called
GRF_GPIO3D_IOMUX. Added definitions allow to configure the SPI0
interface.
BRANCH=none
BUG=chrome-os-partner:50645, chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
communicate over SPI0
Change-Id: Iea92971b0520dc4549cd0fd263dcb2098f80f6d6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349851
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Until now it was assumed that all TPM devices were of the same type
(TCG 1.2 spec compliant) and x86 based boards had LPC connected TPMs
and all other boards had I2C connected TPMs.
With the advent of TPM2 specification there is a need to be able to
configure different combinations of TPM types (TPM or TPM2) and
interfaces (LPC, I2C and SPI).
This patch allows to do it. Picking Chrome OS still assumes that the
board has a TPM device, but adding MAINBOARD_HAS_TPM2 to the board's
Kconfig will trigger including of TPM2 instead.
MAINBOARD_HAS_LPC_TPM forces the interface to be set to LPC, adding
SPI_TPM to the board config switches interface choice to SPI, and if
neither of the two is defined, the interface is assumed to be I2C.
BRANCH=none
BUG=chrome-os-partner:50645
TEST=verified that none of the generated board configurations change
as a result of this patch. With the rest of the stack in place it
is possible to configure different combinations of TPM types and
interfaces for ARM and x86 boards.
Change-Id: I659e9301a4a4fe065ca6537ef1fa824a08d36321
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349850
Reviewed-by: Martin Roth <martinroth@chromium.org>
CBMEM console stores all the console logs in CBMEM. Address of this
location in CBMEM where console logs are stored needs to be passed up to
OS using GNVS.
1. Add CBMC to GNVS fields in globalnvs.asl
2. Add cbmc member to global_nvs_t structure in nvs.h
3. Initialize gnvs->cbmc to address of cbmem console
BUG=chrome-os-partner:54342
Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/353023
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
