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UPSTREAM: Define RAMTOP for x86 only
This Kconfig is deprecated, new platforms need to locate
ramstage stack in CBMEM instead.
Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15189
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry-picked from commit bec853e9ad
)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354180
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
parent
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4 changed files with 5 additions and 14 deletions
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@ -83,6 +83,11 @@ config RAMBASE
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hex
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default 0x100000
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config RAMTOP
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hex
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default 0x200000
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depends on ARCH_X86
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# Traditionally BIOS region on SPI flash boot media was memory mapped right below
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# 4G and it was the last region in the IFD. This way translation between CPU
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# address space to flash address was trivial. However some IFDs on newer SoCs
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@ -44,10 +44,4 @@ config DRAM_SIZE_MB
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int
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default 32768
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# Memory map for qemu power8
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config RAMTOP
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hex
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default 0x1000000
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endif # BOARD_EMULATION_QEMU_POWER8
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@ -54,8 +54,4 @@ config DRAM_SIZE_MB
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# 0x0011_0000: CBFS data
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# 0x0100_0000: reserved for ramstage
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config RAMTOP
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hex
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default 0x1000000
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endif # BOARD_EMULATION_QEMU_UCB_RISCV
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@ -54,8 +54,4 @@ config DRAM_SIZE_MB
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# 0x0011_0000: CBFS data
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# 0x0100_0000: reserved for ramstage
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config RAMTOP
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hex
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default 0x1000000
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endif # BOARD_EMULATION_SPIKE_UCB_RISCV
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