Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: intel/cache_as_ram_ht.inc: Fix include

Browse source 
Reference to CACHE_AS_RAM was from the days we had
romcc boards using socket_mPGA605.

Change-Id: If397db83a01adeda4dd18d8b4c6e89bf0984264a
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15224
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit 831a7ef541)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354185
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-17 20:51:50 +03:00 • committed by chrome-bot
parent b979b55040
commit 3d00092a46
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/cpu/intel/socket_LGA775/Makefile.inc
View file

@ -14,4 +14,4 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc

2
src/cpu/intel/socket_mPGA604/Makefile.inc
View file

@ -9,4 +9,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc