Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

rockchip: rk3399: correct sdram inc file DENALI_CTL_217_DATA value

Browse source 
for per cs training, there should be more cycles to switch delay line.
so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5.

BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass

Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/352953
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
This commit is contained in:
Lin Huang 2016-06-16 10:39:10 +08:00 • committed by chrome-bot
parent e4e9823d8c
commit 9de93beae0
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/gru/sdram_inf/gru-sdram-lpddr3-hynix-4GB.inc
View file

@ -276,7 +276,7 @@
0x04040001, /* DENALI_CTL_214_DATA */
0x0c0c0c04, /* DENALI_CTL_215_DATA */
0x02080808, /* DENALI_CTL_216_DATA */
0x02010103, /* DENALI_CTL_217_DATA */
0x02050103, /* DENALI_CTL_217_DATA */
0x02010103, /* DENALI_CTL_218_DATA */
0x00010103, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */

2
src/mainboard/google/gru/sdram_inf/kevin-sdram-lpddr3-hynix-4GB.inc
View file

@ -275,7 +275,7 @@
0x04030001, /* DENALI_CTL_214_DATA */
0x08080803, /* DENALI_CTL_215_DATA */
0x02080808, /* DENALI_CTL_216_DATA */
0x02010203, /* DENALI_CTL_217_DATA */
0x02050203, /* DENALI_CTL_217_DATA */
0x02010303, /* DENALI_CTL_218_DATA */
0x00010203, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */