Commit graph

56 commits

Author SHA1 Message Date
Corey Osgood
68529567e4 This patch:
* Moves non-DRAM early init code out of initram and into stage1, where 
it should have been in the first place
* Fixes an issue with GP3 timer causing system reboot (possibly not 
present in current svn, but was present in my local copy)
* Fixes serial garbage from stage1 on jetway j7f2
* Fixes ROM mapping for flash > 512k on vt8237
* Makes a couple minor whitespace changes
* Moves some function prototypes to the headers where they belong
* Nukes some phase2 hackery that belongs in phase4 (eventually)
* Comments out early_mtrr_init() for via/epia-cn, this breaks booting on 
jetway j7f2
* Moves troublesome SATA init code into stage1 - change of device class 
hangs coreboot
* Gets to vt8237 IDE phase6 init and dies on jetway/j7f2:
	Phase 6: Initializing devices...                                                
	Phase 6: Root Device init.                                                      
	Phase 6: PCI: 00:10.1 init.                                                     
	Primary IDE interface enabled                                                   
	Secondary IDE interface enabled 
	<hang>

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1070 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-10 21:23:09 +00:00
Myles Watson
7c14a50c1c This patch makes all the SuperIOs build again, and reverts some breakage that
I introduced earlier.

It adds a placeholder in the fintek SuperIO so the array indexing works.
It moves the enable to make the struct more compatible with v2.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1066 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-08 20:40:02 +00:00
Uwe Hermann
09f70836fd This is the first part of a v3 Super I/O refactoring.
Add a small collection of PNP enter/exit functions for many Super I/Os.
Use these functions instead of duplicating them for each chip.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1044 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-18 22:32:05 +00:00
Uwe Hermann
e5fa03aa74 Fix/finish the Winbond W83627THF/THG dts.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1040 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 20:40:39 +00:00
Uwe Hermann
6b0bd8acb7 Fix some incorrect entries in superio/winbond/w83627hf/dts.
The hardware monitor defaults as per datasheet are 0x0000 / 0, but on
hardware that uses this functionality it seems to be 0x290 / 5 often,
thus use those values in the dts.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1034 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 13:45:53 +00:00
Uwe Hermann
c29c991df8 Fix the incorrect VIA VT1211 LDNs, add a comment for each of them.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1033 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 13:41:15 +00:00
Carl-Daniel Hailfinger
0df280f294 Drop duplicated functions from W83627THG SuperI/O stage1 code and fix
up a function prototype.

Fix up #include statements for W83627THG SuperI/O stage2 code.
Use anonymous instead of named unions in struct device.
Point pnp_dev_info members to w83627thg_ops.     
Disable UART and keyboard initialization for now.
Add new code in phase3_chip_setup_dev to fill in configuration values
from the dts (code is partially disabled).

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1032 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 01:52:08 +00:00
Uwe Hermann
7c960311f9 Drop non-working, copy-paste superio.c file (trivial).
The build system isn't even using it so far, but if it would the
build would break (and the code wouldn't work for this hardware).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1030 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-15 16:17:12 +00:00
Myles Watson
18d7d33669 This patch updates the other supported SuperIOs to use the PNP dts changes.
It shouldn't break anything that was working, but I didn't try to fix SuperIOs
that weren't compiling when I started.

Compile tested on 
1. amd/dbm690t for ite/it8712f
2. amp/tinygx for ite/it8716f

I'd already updated fintek/f71805 before I realized jetway doesn't compile.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1028 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 23:03:54 +00:00
Myles Watson
27fbb8428c This patch changes PNP support for devices so that the dts values get passed
in.

include/device/pnp.h:
	Add enable, val, and irq & drq structs.

superio/winbond/w83627hf/superio.c:
	Change functions to operate on children.
	Add device ID to ops.
	Add enables to pnp_dev_info table.
	Fill in dts values.

superio/winbond/w83627hf/dts:
	Get rid of device number parameters.
	Add config parameters so we know when they're set.

device/pnp_device.c:
	Allocate devices as children to SuperIO.

mainboard/amd/serengeti/dts:
	Move ioport so it's found. (Not its permanent resting place I hope.)
	Add enables for KBC, SP1, and HWM to show it off.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1027 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 21:45:10 +00:00
Ronald G. Minnich
adc163d08f This superio is needed for the kontron.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@997 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-12 01:16:22 +00:00
Peter Stuge
a0c86bd24e v3: superio/via/vt1211 with serial port init but nothing else
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@971 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 18:44:57 +00:00
Ronald G. Minnich
07e50cd554 via vt8237, cn700 and jetway j7f2.
Does not yet build

Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@967 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 18:13:20 +00:00
Myles Watson
e7ea68860d Trivial fixes of printk \r\n and white space.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@958 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-28 17:29:07 +00:00
Ronald G. Minnich
cedf16ca69 Marc reviewed the v3 device tree code and we developed the set of
cleanups/fixes.

Fixup device tree code. Add/change methods as needed. 
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-27 20:05:38 +00:00
Corey Osgood
7644420d83 Commit a few things I forgot with the vt8237 patch, and also a couple
minor whitespace fixes I've stumbled accross.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@929 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-15 06:41:16 +00:00
Uwe Hermann
766739b9b8 Fix incorrect and incomplete Fintek F71805F dts. Some LDNs got mixed
up in the dts, some LDNs were missing.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@925 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-14 10:14:06 +00:00
Uwe Hermann
eb08c3a21d Make the ITE IT8712F support in v3 a bit more complete and fix the
incorrect and incomplete pnp_dev_info[] as we did in v2.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@924 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-14 10:13:24 +00:00
Uwe Hermann
1de23d8436 Fix various ITE IT8716F numbers in the dts. Some parts are incorrect,
some are just incomplete.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@923 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-13 21:47:56 +00:00
Corey Osgood
9feee325ff Make some changes to the Fintek F71805f:
* Read port for early serial console from Kconfig
* Change naming from SP (serial port) to COM to be consistent with 
Kconfig

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@917 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-11 17:42:23 +00:00
Corey Osgood
8647942e82 Fix (read: hide) some warning on F71805F until the port gets completed (trivial).
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@914 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-10 20:37:02 +00:00
Ronald G. Minnich
338db28929 Changes to get this wrapped up and compiling.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@897 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-06 17:16:05 +00:00
Ronald G. Minnich
96d8efcb79 Minor typos that need to be fixed. The oddest thing is that an earlier
version, with these typos, compiled. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@889 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-05 04:56:29 +00:00
Ronald G. Minnich
2e5e287aab All superios were broken in v3. Fix them by adding the right node to the
dts and making the ops struct non-static. 

This is the second pass on this patch, I have put the changes in that 
Uwe requested, I hope I got them all. I have not heard back from Uwe yet 
but this patch is urgent. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@888 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-05 04:46:32 +00:00
Ronald G. Minnich
76167990ed Bringing the m57sli to life. This includes changes to mcp55 and
mainboard that we learned with the serengeti that we needed. New 
function in pnp that is for reading. new prototype in pnp.h. New 
constants for ite8716f. 

This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow. 

Now that we have two boards under way we can hopefully see our way to 
getting more put in. The 690 is the obvious next choice. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@876 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 06:47:51 +00:00
Ronald G. Minnich
28ecbeab88 The K8 is one example, but there are other devices (e.g. I2C) that also have
multiple links. The way this was done in v2 was a big confusing; this way is 
less so. 

The changes are easy. Getting them right has been hard :-)

First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0

We have to have the same pcidevfn on these because that is how the k8 works. 
But the unit numbers (pci0, pci1, etc.) distinguish them. 

The dts will properly generate a "v3 device code" 
compatible static tree that puts the links in the right place in the 
data structure. 

The changes to dts are trivial. 
As before, dts nodes with children are understood to be a bridge. 
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};


This entry has no children in the dts. 
How does dt compiler know it is a bridge? It can not know unless 
we add information to the dts for that northbridge part. 
To ensure that all bridge devices are detected, we support the following: 
if a dts node for a device has a bridge property, e.g.: 
 {
        device_operations = "k8_ops";
       bridge;
 };

The dt compiler will treat it as a bridge whether it has children or not. 

Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty, 
or what might be in the socket. 

This code has been tested on dbe62 and k8 simnow, and works on each. 
It is minimal in size and it does what we need. I hope it resolves our 
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!

Also included in this patch are new debug prints in k8 north. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:36:20 +00:00
Carl-Daniel Hailfinger
1b22622323 Change v3 makefile rules to be source-based, part I.
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.

This pepares the way for additional optimizations during compile and
link time.

Build tested and boot tested on Qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 11:15:43 +00:00
Carl-Daniel Hailfinger
77010a1111 The named unions in the device tree code are obnoxious and degrade
readability. Move to anonymous unions.

Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-10 00:20:24 +00:00
Carl-Daniel Hailfinger
1a09707fd6 Convert stage2 and initram makefile rules from object to source files.
This creates a clearer distinction between source files in the source 
tree we want to have compiled and indirectly created object/source files 
in the object tree.

It also will make enable us to move to whole-program 
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as 
well.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 20:56:11 +00:00
Peter Stuge
2a74b39793 v3: Port ITE IT8716F superio code from v2
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@712 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 03:29:02 +00:00
Corey Osgood
855bcc284d Small fixes to make the Fintek F71805f compile (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@645 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-03-24 05:59:53 +00:00
Ronald G. Minnich
57ea42fab8 Fix compilation after switch to explicit dts naming.
One additional cosmetic fix. 

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@569 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-31 03:08:32 +00:00
Stefan Reinauer
6220b632e7 Now version 3: LinuxBIOS -> coreboot rename.
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-27 18:54:57 +00:00
Stefan Reinauer
467102748f I know there is still an ongoing discussion on the list about this patch, and
how support for superios might look in the future. This code (like all the
rest, too) will certainly change and evolve in the future, as v3 evolves.

-----

Add support for the Fintek F71805f to LinuxBIOSv3. It hasn't been tested yet
because something's failing to build elsewhere, but the stage1 does build, and
for the moment that's what matters. It's based on working v2 code so it should
work fine.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@508 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-10-30 02:03:43 +00:00
Stefan Reinauer
0598fd602a This patch removes all printk format warnings from my LBv3 build (Qemu
x86 config). This was tested with gcc 4.1.0 on x86 and gcc 4.2.1 on x86_64.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@466 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-08-11 18:38:24 +00:00
Stefan Reinauer
276a0e0ec9 * move post_code() to a seperate file
* statically link linuxbios.initram for now (depends on printk, post_code
  and die)
* greatly simplify all makefiles by creating a global Rules.make
* use $(dir $@) in Makefiles instead of absolute paths for mkdir..
* clean up Makefiles by calling components' code locally instead of in the
  Makefile. (Remember: one day, no code per mainboard)
* unconditionally create .xcompile in case it changed
* add NM to xcompile                          
* create $(obj)/linuxbios.map with all symbols of all stages

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@463 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-23 16:49:00 +00:00
Uwe Hermann
9779b61f67 Drop a bunch of useless Kconfig files.
Instead of having lots of almost-empty Kconfig files all over the place,
we now collect all the "book-keeping" information (as opposed to real
LinuxBIOS configuration stuff) in one Kconfig file. The benefits are obvious.

Say we have (at some point in the future) 30 supported northbridges, 30
southbridges, and 30 Super I/O chips. That would make 90 useless Kconfig
files with just one or two lines in them, spread all over the place.

With this new approach we would instead have no additional Kconfig
files, just a list of all 90 supported chip(set)s in one Kconfig file.

For "real" config options we would still use Kconfig files in
(e.g.) southbridge/foo/bar/Kconfig, of course, which are manually "hooked"
into the config system in the top-level Kconfig file.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@441 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-10 12:30:07 +00:00
Uwe Hermann
ba2bea5aa5 Drop a bunch of almost-empty Makefiles which are of no real use.
Instead unconditionally include _all_ northbridge/southbridge/superio
Makefiles, but put 'ifeq's in each of them to guard against including
unwanted contents.

This may sound like it's very slow when there are many Makefiles, but in
practice the speed difference is neglectable. A few ad hoc tests I did
showed no measurable speed differences at all (I used 30 or 40 sample
Makefiles).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@440 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-10 12:14:36 +00:00
Stefan Reinauer
fc12d1d148 trivial: fix some dependencies (for make -j)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@436 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-07 09:34:56 +00:00
Uwe Hermann
b3928d6647 Small fix (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@425 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-30 19:37:14 +00:00
Uwe Hermann
c4ae934b2d Various cosmetic fixes in dts files (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@424 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-30 17:50:54 +00:00
Uwe Hermann
c81aa82942 Add an ARRAY_SIZE() macro which returns the size of an array, regardless
of the data types of the individual array elements.

The macro is defined in lib.h, so code which uses it must include lib.h.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@413 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-29 14:36:03 +00:00
Ronald G. Minnich
e62540d291 1. move early_* names to stage1.c
2. rename *_early_init symbols to *_stage1
3. Rename early_init to hardware_stage1

now people can see when things are supposed to happen. 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@407 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-29 00:09:24 +00:00
Uwe Hermann
2a605775a6 Various cosmetic license header fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@392 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-28 14:06:39 +00:00
Ronald G. Minnich
bf3105afb9 In reponse to comments.
We are leaving serial, we do not believe it is misleading. 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@383 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-27 20:44:02 +00:00
Ronald G. Minnich
84448165f9 Superio commits.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@380 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-27 20:09:47 +00:00
Uwe Hermann
464ef4613d Use the same naming convention and placement for "include guards" in
all header files.

This closes #40, as I think we don't need to invest time to fix this in
LinuxBIOSv2, but only in LinuxBIOSv3.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@332 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-05-21 06:48:47 +00:00
Uwe Hermann
53099f8d1c Fix various license headers.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@330 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-05-20 20:35:59 +00:00
Uwe Hermann
71ccb36afc Massive file rename and moving orgy:
- Everything in include/cpu/generic/x86/arch/* goes into
   include/arch/x86 now.

 - include/cpu/generic/x86/div64.h moves into include/arch/x86, too.

 - The former include/cpu/generic/x86/arch/elf.h moved to
   include/arch/x86/archelf.h, as elf.h already exists in include/
   and we must prevent a name clash.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@314 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-05-05 21:36:52 +00:00
Uwe Hermann
7e752a0631 Move include/console/console.h to include/console.h in order to
get rid of a directory which only contains a single file, and
at the same time simplify the #includes and their hierarchies.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@313 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-05-05 20:18:28 +00:00