mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This patch makes all the SuperIOs build again, and reverts some breakage that
I introduced earlier. It adds a placeholder in the fintek SuperIO so the array indexing works. It moves the enable to make the struct more compatible with v2. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1066 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson
parent
f7a5eaf57e
commit
7c14a50c1c
8 changed files with 131 additions and 144 deletions
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@ -57,7 +57,7 @@ void pnp_set_enable(struct device *dev, int enable)
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int pnp_read_enable(struct device *dev)
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{
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return !!pnp_read_config(dev, 0x30);
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return (pnp_read_config(dev, 0x30) ? 0x1 : 0x0);
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}
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void pnp_set_iobase(struct device *dev, unsigned int index, unsigned int iobase)
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@ -110,7 +110,7 @@ static void pnp_set_resource(struct device *dev, struct resource *resource)
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}
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resource->flags |= IORESOURCE_STORED;
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report_resource_stored(dev, resource, "");
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report_resource_stored(dev, resource, __func__);
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}
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void pnp_set_resources(struct device *dev)
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@ -192,7 +192,7 @@ static void pnp_get_ioresource(struct device *dev, unsigned int index,
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resource->limit = info->mask | (step - 1);
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resource->size = 1 << gran;
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resource->base = info->val;
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resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
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resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
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}
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static void get_resources(struct device *dev, struct pnp_info *info)
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@ -215,29 +215,29 @@ static void get_resources(struct device *dev, struct pnp_info *info)
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resource = new_resource(dev, PNP_IDX_IRQ0);
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resource->size = 1;
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resource->flags |= IORESOURCE_IRQ;
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resource->base = info->irq0.val;
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resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
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resource->base = info->irq0;
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resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
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}
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if (info->flags & PNP_IRQ1) {
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resource = new_resource(dev, PNP_IDX_IRQ1);
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resource->size = 1;
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resource->flags |= IORESOURCE_IRQ;
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resource->base = info->irq1.val;
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resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
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resource->base = info->irq1;
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resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
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}
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if (info->flags & PNP_DRQ0) {
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resource = new_resource(dev, PNP_IDX_DRQ0);
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resource->size = 1;
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resource->flags |= IORESOURCE_DRQ;
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resource->base = info->drq0.val;
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resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
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resource->base = info->drq0;
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resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
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}
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if (info->flags & PNP_DRQ1) {
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resource = new_resource(dev, PNP_IDX_DRQ1);
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resource->size = 1;
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resource->flags |= IORESOURCE_DRQ;
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resource->base = info->drq0.val;
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resource->flags |= IORESOURCE_FIXED || IORESOURCE_ASSIGNED;
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resource->base = info->drq0;
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resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
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}
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}
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@ -254,6 +254,7 @@ void pnp_enable_devices(struct device *base_dev, struct device_operations *ops,
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/* Setup the ops and resources on the newly allocated devices. */
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for (i = 0; i < functions; i++) {
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path.pnp.device = info[i].function;
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dev = find_dev_path(&base_dev->link[0], &path);
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@ -263,7 +264,7 @@ void pnp_enable_devices(struct device *base_dev, struct device_operations *ops,
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__func__, dev->dtsname, dev_path(dev));
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continue;
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}
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dev = alloc_dev(&base_dev->link[0], &path, &id);
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if (!dev)
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@ -310,12 +311,12 @@ static void pnp_enter_ite_legacy(struct device *dev, const u8 init[][4])
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{
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int i, idx;
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u16 port = dev->path.pnp.port;
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/* Determine Super I/O config port. */
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idx = (port == 0x3f0) ? 0 : ((port == 0x3bd) ? 1 : 2);
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for (i = 0; i < 4; i++)
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outb(init[idx][i], ISA_PNP_ADDR);
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/* Sequentially write the 32 MB PnP init values. */
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for (i = 0; i < 32; i++)
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outb(initkey_mbpnp[i], port);
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@ -59,7 +59,6 @@ struct io_info {
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struct pnp_info {
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struct device_operations *ops;
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unsigned function;
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unsigned enable;
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unsigned flags;
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#define PNP_IO0 0x01
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#define PNP_IO1 0x02
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@ -69,11 +68,15 @@ struct pnp_info {
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#define PNP_IRQ1 0x20
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#define PNP_DRQ0 0x40
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#define PNP_DRQ1 0x80
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struct io_info io0, io1, io2, io3, irq0, irq1, drq0, drq1;
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struct io_info io0, io1, io2, io3;
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unsigned irq0, irq1, drq0, drq1;
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unsigned enable;
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};
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struct resource *pnp_get_resource(struct device * dev, unsigned index);
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void pnp_enable_devices(struct device *dev, struct device_operations *ops,
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unsigned functions, struct pnp_info *info);
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unsigned functions, struct pnp_info *info);
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#define PNP_IDX_IO0 0x60
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#define PNP_IDX_IO1 0x62
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@ -93,6 +93,8 @@ struct device_operations f71805f_ops = {
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};
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static struct pnp_info pnp_dev_info[] = {
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/* Ops, function #, All resources needed by dev, io_info */
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{ NULL, F71805F_FDC, }, /* Place holder. */
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{ &f71805f_ops, F71805F_COM1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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{ &f71805f_ops, F71805F_COM2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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/* TODO: Everything else */
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@ -106,12 +108,12 @@ static void phase2_setup_scan_bus(struct device *dev)
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/* COM1 */
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pnp_dev_info[F71805F_COM1].enable = conf->com1enable;
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pnp_dev_info[F71805F_COM1].io0.val = conf->com1io;
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pnp_dev_info[F71805F_COM1].irq0.val = conf->com1irq;
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pnp_dev_info[F71805F_COM1].irq0 = conf->com1irq;
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/* COM2 */
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pnp_dev_info[F71805F_COM2].enable = conf->com2enable;
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pnp_dev_info[F71805F_COM2].io0.val = conf->com2io;
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pnp_dev_info[F71805F_COM2].irq0.val = conf->com2irq;
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pnp_dev_info[F71805F_COM2].irq0 = conf->com2irq;
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/* Initialize SuperIO for PNP children. */
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if (!dev->links) {
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@ -95,18 +95,18 @@ struct device_operations it8712f_ops = {
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};
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static struct pnp_info pnp_dev_info[] = {
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/* Enable, All resources need by dev, io_info_structs */
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{&it8712f_ops, IT8712F_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},},
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{&it8712f_ops, IT8712F_SP1, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
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{&it8712f_ops, IT8712F_SP2, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
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{&it8712f_ops, IT8712F_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},},
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{&it8712f_ops, IT8712F_EC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},},
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{&it8712f_ops, IT8712F_KBCK, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},},
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{&it8712f_ops, IT8712F_KBCM, 0, PNP_IRQ0,},
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{&it8712f_ops, IT8712F_GPIO, 0, },
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{&it8712f_ops, IT8712F_MIDI, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
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{&it8712f_ops, IT8712F_GAME, 0, PNP_IO0, {0xfff, 0},},
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{&it8712f_ops, IT8712F_IR, 0, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
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/* All resources needed by dev, io_info_structs */
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{&it8712f_ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},},
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{&it8712f_ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
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{&it8712f_ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
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{&it8712f_ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},},
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{&it8712f_ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},},
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{&it8712f_ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},},
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{&it8712f_ops, IT8712F_KBCM, PNP_IRQ0,},
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{&it8712f_ops, IT8712F_GPIO, },
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{&it8712f_ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
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{&it8712f_ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},},
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{&it8712f_ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
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};
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static void it8712f_setup_scan_bus(struct device *dev)
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@ -116,38 +116,38 @@ static void it8712f_setup_scan_bus(struct device *dev)
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/* Floppy */
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pnp_dev_info[IT8712F_FDC].enable = conf->floppyenable;
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pnp_dev_info[IT8712F_FDC].io0.val = conf->floppyio;
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pnp_dev_info[IT8712F_FDC].irq0.val = conf->floppyirq;
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pnp_dev_info[IT8712F_FDC].drq0.val = conf->floppydrq;
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pnp_dev_info[IT8712F_FDC].irq0 = conf->floppyirq;
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pnp_dev_info[IT8712F_FDC].drq0 = conf->floppydrq;
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/* COM1 */
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pnp_dev_info[IT8712F_SP1].enable = conf->com1enable;
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pnp_dev_info[IT8712F_SP1].io0.val = conf->com1io;
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pnp_dev_info[IT8712F_SP1].irq0.val = conf->com1irq;
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pnp_dev_info[IT8712F_SP1].irq0 = conf->com1irq;
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/* COM2 */
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pnp_dev_info[IT8712F_SP2].enable = conf->com2enable;
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pnp_dev_info[IT8712F_SP2].io0.val = conf->com2io;
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pnp_dev_info[IT8712F_SP2].irq0.val = conf->com2irq;
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pnp_dev_info[IT8712F_SP2].irq0 = conf->com2irq;
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/* Parallel port */
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pnp_dev_info[IT8712F_PP].enable = conf->ppenable;
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pnp_dev_info[IT8712F_PP].io0.val = conf->ppio;
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pnp_dev_info[IT8712F_PP].irq0.val = conf->ppirq;
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pnp_dev_info[IT8712F_PP].irq0 = conf->ppirq;
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/* Environment controller */
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pnp_dev_info[IT8712F_EC].enable = conf->ecenable;
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pnp_dev_info[IT8712F_EC].io0.val = conf->ecio;
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pnp_dev_info[IT8712F_EC].irq0.val = conf->ecirq;
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pnp_dev_info[IT8712F_EC].irq0 = conf->ecirq;
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/* Keyboard */
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pnp_dev_info[IT8712F_KBCK].enable = conf->kbenable;
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pnp_dev_info[IT8712F_KBCK].io0.val = conf->kbio;
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pnp_dev_info[IT8712F_KBCK].io1.val = conf->kbio2;
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pnp_dev_info[IT8712F_KBCK].irq0.val = conf->kbirq;
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pnp_dev_info[IT8712F_KBCK].irq0 = conf->kbirq;
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/* PS/2 mouse */
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pnp_dev_info[IT8712F_KBCM].enable = conf->mouseenable;
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pnp_dev_info[IT8712F_KBCM].irq0.val = conf->mouseirq;
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pnp_dev_info[IT8712F_KBCM].irq0 = conf->mouseirq;
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/* GPIO */
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pnp_dev_info[IT8712F_GPIO].enable = conf->gpioenable;
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@ -155,7 +155,7 @@ static void it8712f_setup_scan_bus(struct device *dev)
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/* MIDI port */
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pnp_dev_info[IT8712F_MIDI].enable = conf->midienable;
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pnp_dev_info[IT8712F_MIDI].io0.val = conf->midiio;
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pnp_dev_info[IT8712F_MIDI].irq0.val = conf->midiirq;
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pnp_dev_info[IT8712F_MIDI].irq0 = conf->midiirq;
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/* Game port */
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pnp_dev_info[IT8712F_GAME].enable = conf->gameenable;
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@ -164,7 +164,7 @@ static void it8712f_setup_scan_bus(struct device *dev)
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/* Consumer IR */
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pnp_dev_info[IT8712F_IR].enable = conf->cirenable;
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pnp_dev_info[IT8712F_IR].io0.val = conf->cirio;
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pnp_dev_info[IT8712F_IR].irq0.val = conf->cirirq;
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pnp_dev_info[IT8712F_IR].irq0 = conf->cirirq;
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/* Initialize SuperIO for PNP children. */
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if (!dev->links) {
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@ -133,20 +133,20 @@ struct device_operations it8716f_ops = {
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};
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static struct pnp_info pnp_dev_info[] = {
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/* Enable, All resources need by dev, io_info_structs */
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{&it8716f_ops, IT8716F_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&it8716f_ops, IT8716F_SP1, 0, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_SP2, 0, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&it8716f_ops, IT8716F_EC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
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/* All resources needed by dev, io_info_structs */
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{&it8716f_ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&it8716f_ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
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{&it8716f_ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
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{0x7f8, 0x4},},
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{&it8716f_ops, IT8716F_KBCK, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
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{&it8716f_ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
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{0x7ff, 0x4},},
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{&it8716f_ops, IT8716F_KBCM, 0, PNP_IRQ0,},
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{&it8716f_ops, IT8716F_GPIO, 0, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_MIDI, 0, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
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{&it8716f_ops, IT8716F_GAME, 0, PNP_IO0, {0x7ff, 0},},
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{&it8716f_ops, IT8716F_IR, 0,},
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{&it8716f_ops, IT8716F_KBCM, PNP_IRQ0,},
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{&it8716f_ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
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{&it8716f_ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
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{&it8716f_ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
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{&it8716f_ops, IT8716F_IR, },
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};
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static void it8716f_setup_scan_bus(struct device *dev)
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@ -156,38 +156,38 @@ static void it8716f_setup_scan_bus(struct device *dev)
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/* Floppy */
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pnp_dev_info[IT8716F_FDC].enable = conf->floppyenable;
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pnp_dev_info[IT8716F_FDC].io0.val = conf->floppyio;
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pnp_dev_info[IT8716F_FDC].irq0.val = conf->floppyirq;
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pnp_dev_info[IT8716F_FDC].drq0.val = conf->floppydrq;
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pnp_dev_info[IT8716F_FDC].irq0 = conf->floppyirq;
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pnp_dev_info[IT8716F_FDC].drq0 = conf->floppydrq;
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/* COM1 */
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pnp_dev_info[IT8716F_SP1].enable = conf->com1enable;
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pnp_dev_info[IT8716F_SP1].io0.val = conf->com1io;
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pnp_dev_info[IT8716F_SP1].irq0.val = conf->com1irq;
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pnp_dev_info[IT8716F_SP1].irq0 = conf->com1irq;
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/* COM2 */
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pnp_dev_info[IT8716F_SP2].enable = conf->com2enable;
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pnp_dev_info[IT8716F_SP2].io0.val = conf->com2io;
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pnp_dev_info[IT8716F_SP2].irq0.val = conf->com2irq;
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pnp_dev_info[IT8716F_SP2].irq0 = conf->com2irq;
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/* Parallel port */
|
||||
pnp_dev_info[IT8716F_PP].enable = conf->ppenable;
|
||||
pnp_dev_info[IT8716F_PP].io0.val = conf->ppio;
|
||||
pnp_dev_info[IT8716F_PP].irq0.val = conf->ppirq;
|
||||
pnp_dev_info[IT8716F_PP].irq0 = conf->ppirq;
|
||||
|
||||
/* Environment controller */
|
||||
pnp_dev_info[IT8716F_EC].enable = conf->ecenable;
|
||||
pnp_dev_info[IT8716F_EC].io0.val = conf->ecio;
|
||||
pnp_dev_info[IT8716F_EC].irq0.val = conf->ecirq;
|
||||
pnp_dev_info[IT8716F_EC].irq0 = conf->ecirq;
|
||||
|
||||
/* Keyboard */
|
||||
pnp_dev_info[IT8716F_KBCK].enable = conf->kbenable;
|
||||
pnp_dev_info[IT8716F_KBCK].io0.val = conf->kbio;
|
||||
pnp_dev_info[IT8716F_KBCK].io1.val = conf->kbio2;
|
||||
pnp_dev_info[IT8716F_KBCK].irq0.val = conf->kbirq;
|
||||
pnp_dev_info[IT8716F_KBCK].irq0 = conf->kbirq;
|
||||
|
||||
/* PS/2 mouse */
|
||||
pnp_dev_info[IT8716F_KBCM].enable = conf->mouseenable;
|
||||
pnp_dev_info[IT8716F_KBCM].irq0.val = conf->mouseirq;
|
||||
pnp_dev_info[IT8716F_KBCM].irq0 = conf->mouseirq;
|
||||
|
||||
/* GPIO */
|
||||
pnp_dev_info[IT8716F_GPIO].enable = conf->gpioenable;
|
||||
|
|
@ -195,7 +195,7 @@ static void it8716f_setup_scan_bus(struct device *dev)
|
|||
/* MIDI port */
|
||||
pnp_dev_info[IT8716F_MIDI].enable = conf->midienable;
|
||||
pnp_dev_info[IT8716F_MIDI].io0.val = conf->midiio;
|
||||
pnp_dev_info[IT8716F_MIDI].irq0.val = conf->midiirq;
|
||||
pnp_dev_info[IT8716F_MIDI].irq0 = conf->midiirq;
|
||||
|
||||
/* Game port */
|
||||
pnp_dev_info[IT8716F_GAME].enable = conf->gameenable;
|
||||
|
|
@ -204,7 +204,7 @@ static void it8716f_setup_scan_bus(struct device *dev)
|
|||
/* Consumer IR */
|
||||
pnp_dev_info[IT8716F_IR].enable = conf->cirenable;
|
||||
pnp_dev_info[IT8716F_IR].io0.val = conf->cirio;
|
||||
pnp_dev_info[IT8716F_IR].irq0.val = conf->cirirq;
|
||||
pnp_dev_info[IT8716F_IR].irq0 = conf->cirirq;
|
||||
|
||||
/* Initialize SuperIO for PNP children. */
|
||||
if (!dev->links) {
|
||||
|
|
|
|||
|
|
@ -195,22 +195,21 @@ struct device_operations w83627hf_ops = {
|
|||
};
|
||||
|
||||
static struct pnp_info pnp_dev_info[] = {
|
||||
/* Enable, All resources need by dev, io_info_structs */
|
||||
{ &w83627hf_ops, W83627HF_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &w83627hf_ops, W83627HF_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &w83627hf_ops, W83627HF_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ &w83627hf_ops, W83627HF_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ 0,},
|
||||
{ &w83627hf_ops, W83627HF_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
|
||||
{ &w83627hf_ops, W83627HF_CIR, 0,PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, 0,PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
|
||||
{ &w83627hf_ops, W83627HF_GPIO2, 0 },
|
||||
{ &w83627hf_ops, W83627HF_GPIO3, 0 },
|
||||
{ &w83627hf_ops, W83627HF_ACPI, 0 },
|
||||
{ &w83627hf_ops, W83627HF_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
|
||||
/* Ops, function #, All resources needed by dev, io_info_structs */
|
||||
{ &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ 0, }, /* No function 4. */
|
||||
{ &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
|
||||
{ &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
|
||||
{ &w83627hf_ops, W83627HF_GPIO2, },
|
||||
{ &w83627hf_ops, W83627HF_GPIO3, },
|
||||
{ &w83627hf_ops, W83627HF_ACPI, },
|
||||
{ &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
|
||||
};
|
||||
|
||||
|
||||
static void phase3_chip_setup_dev(struct device *dev)
|
||||
{
|
||||
/* Get dts values and populate pnp_dev_info. */
|
||||
|
|
@ -219,30 +218,30 @@ static void phase3_chip_setup_dev(struct device *dev)
|
|||
/* Floppy */
|
||||
pnp_dev_info[W83627HF_FDC].enable = conf->floppyenable;
|
||||
pnp_dev_info[W83627HF_FDC].io0.val = conf->floppyio;
|
||||
pnp_dev_info[W83627HF_FDC].irq0.val = conf->floppyirq;
|
||||
pnp_dev_info[W83627HF_FDC].drq0.val = conf->floppydrq;
|
||||
pnp_dev_info[W83627HF_FDC].irq0 = conf->floppyirq;
|
||||
pnp_dev_info[W83627HF_FDC].drq0 = conf->floppydrq;
|
||||
|
||||
/* Parallel port */
|
||||
pnp_dev_info[W83627HF_PP].enable = conf->ppenable;
|
||||
pnp_dev_info[W83627HF_PP].io0.val = conf->ppio;
|
||||
pnp_dev_info[W83627HF_PP].irq0.val = conf->ppirq;
|
||||
pnp_dev_info[W83627HF_PP].irq0 = conf->ppirq;
|
||||
|
||||
/* COM1 */
|
||||
pnp_dev_info[W83627HF_SP1].enable = conf->com1enable;
|
||||
pnp_dev_info[W83627HF_SP1].io0.val = conf->com1io;
|
||||
pnp_dev_info[W83627HF_SP1].irq0.val = conf->com1irq;
|
||||
pnp_dev_info[W83627HF_SP1].irq0 = conf->com1irq;
|
||||
|
||||
/* COM2 */
|
||||
pnp_dev_info[W83627HF_SP2].enable = conf->com2enable;
|
||||
pnp_dev_info[W83627HF_SP2].io0.val = conf->com2io;
|
||||
pnp_dev_info[W83627HF_SP2].irq0.val = conf->com2irq;
|
||||
pnp_dev_info[W83627HF_SP2].irq0 = conf->com2irq;
|
||||
|
||||
/* Keyboard */
|
||||
pnp_dev_info[W83627HF_KBC].enable = conf->kbenable;
|
||||
pnp_dev_info[W83627HF_KBC].io0.val = conf->kbio;
|
||||
pnp_dev_info[W83627HF_KBC].io1.val = conf->kbio2;
|
||||
pnp_dev_info[W83627HF_KBC].irq0.val = conf->kbirq;
|
||||
pnp_dev_info[W83627HF_KBC].irq1.val = conf->kbirq2;
|
||||
pnp_dev_info[W83627HF_KBC].irq0 = conf->kbirq;
|
||||
pnp_dev_info[W83627HF_KBC].irq1 = conf->kbirq2;
|
||||
|
||||
/* Consumer IR */
|
||||
pnp_dev_info[W83627HF_CIR].enable = conf->cirenable;
|
||||
|
|
@ -251,7 +250,7 @@ static void phase3_chip_setup_dev(struct device *dev)
|
|||
pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].enable = conf->gameenable;
|
||||
pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].io0.val = conf->gameio;
|
||||
pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].io1.val = conf->gameio2;
|
||||
pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].irq0.val = conf->gameirq;
|
||||
pnp_dev_info[W83627HF_GAME_MIDI_GPIO1].irq0 = conf->gameirq;
|
||||
|
||||
/* GPIO2 */
|
||||
pnp_dev_info[W83627HF_GPIO2].enable = conf->gpio2enable;
|
||||
|
|
@ -265,7 +264,7 @@ static void phase3_chip_setup_dev(struct device *dev)
|
|||
/* Hardware Monitor */
|
||||
pnp_dev_info[W83627HF_HWM].enable = conf->hwmenable;
|
||||
pnp_dev_info[W83627HF_HWM].io0.val = conf->hwmio;
|
||||
pnp_dev_info[W83627HF_HWM].irq0.val = conf->hwmirq;
|
||||
pnp_dev_info[W83627HF_HWM].irq0 = conf->hwmirq;
|
||||
|
||||
/* Initialize SuperIO for PNP children. */
|
||||
if (!dev->links) {
|
||||
|
|
@ -275,7 +274,6 @@ static void phase3_chip_setup_dev(struct device *dev)
|
|||
dev->link[0].link = 0;
|
||||
}
|
||||
|
||||
/* Call init with updated tables to create children. */
|
||||
/* Call init with updated tables to create and enable children. */
|
||||
pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -24,33 +24,28 @@
|
|||
/* To override any of these, put the over-ride in mainboard dts. */
|
||||
|
||||
/* Floppy */
|
||||
floppydev = "0";
|
||||
floppyenable = "0";
|
||||
floppyio = "0x3f0";
|
||||
floppyirq = "6";
|
||||
floppydrq = "2";
|
||||
|
||||
/* Parallel port */
|
||||
ppdev = "1";
|
||||
ppenable = "0";
|
||||
ppio = "0x378";
|
||||
ppirq = "7";
|
||||
ppdrq = "4";
|
||||
|
||||
/* COM1 */
|
||||
com1dev = "2";
|
||||
com1enable = "0";
|
||||
com1io = "0x3f8";
|
||||
com1irq = "4";
|
||||
|
||||
/* COM2 */
|
||||
com2dev = "3";
|
||||
com2enable = "0";
|
||||
com2io = "0x2f8";
|
||||
com2irq = "3";
|
||||
|
||||
/* PS/2 keyboard + PS/2 mouse */
|
||||
kbdev = "5";
|
||||
kbenable = "0";
|
||||
kbio = "0x60";
|
||||
kbio2 = "0x64";
|
||||
|
|
@ -58,26 +53,21 @@
|
|||
kbirq2 = "12";
|
||||
|
||||
/* Game port, MIDI port, GPIO1, GPIO5 */
|
||||
gamedev = "7";
|
||||
gameenable = "0";
|
||||
gameio = "0x201";
|
||||
gameio2 = "0x330";
|
||||
gameirq = "9";
|
||||
|
||||
/* GPIO2 */
|
||||
gpio2dev = "8";
|
||||
gpio2enable = "0";
|
||||
|
||||
/* GPIO3, GPIO4 */
|
||||
gpio34dev = "9";
|
||||
gpio34enable = "0";
|
||||
|
||||
/* ACPI */
|
||||
acpidev = "10";
|
||||
acpienable = "0";
|
||||
|
||||
/* Hardware Monitor */
|
||||
hwmdev = "11";
|
||||
hwmenable = "0";
|
||||
hwmio = "0x290";
|
||||
hwmirq = "5";
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2000 AG Electronics Ltd.
|
||||
* Copyright 2000 AG Electronics Ltd.
|
||||
* Copyright 2003-2004 Linux Networx
|
||||
* Copyright 2004 Tyan
|
||||
* Copyright 2004 Tyan
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
|
|
@ -25,10 +25,8 @@
|
|||
#include <device/pnp.h>
|
||||
#include <console.h>
|
||||
#include <string.h>
|
||||
//#include <bitops.h>
|
||||
#include <uart8250.h>
|
||||
#include <keyboard.h>
|
||||
// #include <pc80/mc146818rtc.h>
|
||||
#include <statictree.h>
|
||||
#include "w83627thg.h"
|
||||
|
||||
|
|
@ -93,17 +91,19 @@ struct device_operations w83627thg_ops = {
|
|||
|
||||
/* TODO: this device is not at all filled out. Just copied from v2. */
|
||||
static struct pnp_info pnp_dev_info[] = {
|
||||
{ &w83627thg_ops, W83627THG_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &w83627thg_ops, W83627THG_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &w83627thg_ops, W83627THG_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ &w83627thg_ops, W83627THG_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
// No 4 { 0,},
|
||||
{ &w83627thg_ops, W83627THG_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
|
||||
{ &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
|
||||
{ &w83627thg_ops, W83627THG_GPIO2,},
|
||||
{ &w83627thg_ops, W83627THG_GPIO3,},
|
||||
{ &w83627thg_ops, W83627THG_ACPI, 0, PNP_IRQ0, },
|
||||
{ &w83627thg_ops, W83627THG_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
|
||||
/* Ops, function #, All resources needed by dev, io_info_structs */
|
||||
{ &w83627thg_ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &w83627thg_ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
|
||||
{ &w83627thg_ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ &w83627thg_ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
|
||||
{ 0, }, /* No function 4. */
|
||||
{ &w83627thg_ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
|
||||
{ 0, }, /* No function 6. */
|
||||
{ &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
|
||||
{ &w83627thg_ops, W83627THG_GPIO2, },
|
||||
{ &w83627thg_ops, W83627THG_GPIO3, },
|
||||
{ &w83627thg_ops, W83627THG_ACPI, },
|
||||
{ &w83627thg_ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
|
||||
};
|
||||
|
||||
static void phase3_chip_setup_dev(struct device *dev)
|
||||
|
|
@ -111,33 +111,45 @@ static void phase3_chip_setup_dev(struct device *dev)
|
|||
/* Get dts values and populate pnp_dev_info. */
|
||||
const struct superio_winbond_w83627thg_dts_config * const conf = dev->device_configuration;
|
||||
|
||||
#if 0
|
||||
These are not set up at all v2. Ignore for now. */
|
||||
/* Floppy */
|
||||
pnp_dev_info[W83627THG_FDC].enable = conf->floppyenable;
|
||||
pnp_dev_info[W83627THG_FDC].io0.val = conf->floppyio;
|
||||
pnp_dev_info[W83627THG_FDC].irq0.val = conf->floppyirq;
|
||||
pnp_dev_info[W83627THG_FDC].drq0.val = conf->floppydrq;
|
||||
pnp_dev_info[W83627THG_FDC].irq0 = conf->floppyirq;
|
||||
pnp_dev_info[W83627THG_FDC].drq0 = conf->floppydrq;
|
||||
|
||||
/* Parallel port */
|
||||
pnp_dev_info[W83627THG_PP].enable = conf->ppenable;
|
||||
pnp_dev_info[W83627THG_PP].io0.val = conf->ppio;
|
||||
pnp_dev_info[W83627THG_PP].irq0.val = conf->ppirq;
|
||||
pnp_dev_info[W83627THG_PP].irq0 = conf->ppirq;
|
||||
|
||||
/* Consumer IR */
|
||||
pnp_dev_info[W83627THG_CIR].enable = conf->cirenable;
|
||||
/* COM1 */
|
||||
pnp_dev_info[W83627THG_SP1].enable = conf->com1enable;
|
||||
pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io;
|
||||
pnp_dev_info[W83627THG_SP1].irq0 = conf->com1irq;
|
||||
|
||||
/* COM2 */
|
||||
pnp_dev_info[W83627THG_SP2].enable = conf->com2enable;
|
||||
pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io;
|
||||
pnp_dev_info[W83627THG_SP2].irq0 = conf->com2irq;
|
||||
|
||||
/* Keyboard */
|
||||
pnp_dev_info[W83627THG_KBC].enable = conf->kbenable;
|
||||
pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio;
|
||||
pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2;
|
||||
pnp_dev_info[W83627THG_KBC].irq0 = conf->kbirq;
|
||||
pnp_dev_info[W83627THG_KBC].irq1 = conf->kbirq2;
|
||||
|
||||
/* Game port */
|
||||
pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].enable = conf->gameenable;
|
||||
pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io0.val = conf->gameio;
|
||||
pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io1.val = conf->gameio2;
|
||||
pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0.val = conf->gameirq;
|
||||
pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0 = conf->gameirq;
|
||||
|
||||
/* GPIO2 */
|
||||
pnp_dev_info[W83627THG_GPIO2].enable = conf->gpio2enable;
|
||||
|
||||
/* GPIO3 */
|
||||
pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio3enable;
|
||||
/* GPIO3, GPIO4 */
|
||||
pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio34enable;
|
||||
|
||||
/* ACPI */
|
||||
pnp_dev_info[W83627THG_ACPI].enable = conf->acpienable;
|
||||
|
|
@ -145,26 +157,7 @@ These are not set up at all v2. Ignore for now. */
|
|||
/* Hardware Monitor */
|
||||
pnp_dev_info[W83627THG_HWM].enable = conf->hwmenable;
|
||||
pnp_dev_info[W83627THG_HWM].io0.val = conf->hwmio;
|
||||
pnp_dev_info[W83627THG_HWM].irq0.val = conf->hwmirq;
|
||||
|
||||
#endif
|
||||
|
||||
/* COM1 */
|
||||
pnp_dev_info[W83627THG_SP1].enable = conf->com1enable;
|
||||
pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io;
|
||||
pnp_dev_info[W83627THG_SP1].irq0.val = conf->com1irq;
|
||||
|
||||
/* COM2 */
|
||||
pnp_dev_info[W83627THG_SP2].enable = conf->com2enable;
|
||||
pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io;
|
||||
pnp_dev_info[W83627THG_SP2].irq0.val = conf->com2irq;
|
||||
|
||||
/* Keyboard */
|
||||
pnp_dev_info[W83627THG_KBC].enable = conf->kbenable;
|
||||
pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio;
|
||||
pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2;
|
||||
pnp_dev_info[W83627THG_KBC].irq0.val = conf->kbirq;
|
||||
pnp_dev_info[W83627THG_KBC].irq1.val = conf->kbirq2;
|
||||
pnp_dev_info[W83627THG_HWM].irq0 = conf->hwmirq;
|
||||
|
||||
/* Initialize SuperIO for PNP children. */
|
||||
if (!dev->links) {
|
||||
|
|
@ -174,6 +167,6 @@ These are not set up at all v2. Ignore for now. */
|
|||
dev->link[0].link = 0;
|
||||
}
|
||||
|
||||
/* Call init with updated tables to create children. */
|
||||
/* Call init with updated tables to create and enable children. */
|
||||
pnp_enable_devices(dev, &w83627thg_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue