Commit graph

110 commits

Author SHA1 Message Date
Myles Watson
9d6d811dd1 This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1131 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-12 21:15:34 +00:00
Mart Raudsepp
d7048f10ca cs5536: Fix NAND Flash setup.
A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach
the NAND controller. Only NAND controller, as the only DIVIL component that is
allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals
(that are separate GLIU devices outside DIVIL component) can use addresses above
that limit (see in-code comment for details).

In combination with a new VSA2 version 1.02 or newer, this makes NAND flash
finally work in coreboot v3.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1125 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-09 16:10:58 +00:00
Mart Raudsepp
fdc00efeef cs5536: Use NANDF_CTL for NAND Flash Control Timing register constant 5140001Ch define, as in data book, not mis-spelled NADF_CNTL
Trivial: constant currently not used anywhere.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1124 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-09 13:40:10 +00:00
Marc Jones
70b7967bb6 Fix rs690 bug about GPPSB configuration.
Signed-off-by:  Maggie Li <maggie.li@amd.com>
Reviewed-by:    Zheng Bao <Zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1123 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-23 22:18:24 +00:00
Mart Raudsepp
cb5d9d3867 cs5536: Remove redundant enable_ide variable from ide device.
The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form.
cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't
exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not
necessary.
Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole
IDE device removed, which results in the ide_init() code not being ran as before (before it was called but
early return from enable_ide == 0, now it won't be called in the first place).

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-09 18:12:08 +00:00
Mart Raudsepp
3538adacfb cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better.
It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late
before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2
before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it
enabled in VSA2.
It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch,
but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the
VSA2 bug suggests something further will still need fixing. There are also more potential opportunities
to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup
actually works right in the current form.

Also corrected the documentation of ide_init() to match current reality.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1113 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-09 18:12:05 +00:00
Myles Watson
9e1275fd39 This patch does some minor fixups for 8111 and 8132 and adds support for 8131.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1098 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-05 23:02:16 +00:00
Myles Watson
754ef311d4 patch: geodelx.diff
This patch fixes up geode for the new resource allocator.  This is the
bare minimum.  I think the functions of the northbridge should be split based
on whether they are domain-specific or not.

southbridge/amd/cs5536/cs5536.c:
	Change read resources to add a fixed IO resource for legacy decoding.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1091 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-31 19:56:11 +00:00
Myles Watson
d4480beaec specific-resources.diff:
This patch makes specific devices use the updated resource allocation code.

The changes necessary are:
	1. Remove all calls to compute_allocate_resources.
	2. Don't store resources except in phase4_set_resources.

northbridge/amd/k8/pci.c:
	Remove calls to compute_allocate_resource.
	Change phase4_assign_resources to phase4_set_resources

southbridge/amd/amd8132/amd8132_bridge.c:
	Remove NPUML and NPUMB.
	Add a warning for bus disabling.
	Remove bridge_{read|set}_resources (they were there for NPUML)
	
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
	Remove references to have_resources.

southbridge/amd/amd8111/lpc.c:
	Add resources for subtractive IO and ROM.

northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
	Change phase4_assign_resources->phase4_set_resources.
	
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-31 19:46:14 +00:00
Myles Watson
3169211c8b This patch makes the 8151 compile and adds it to the amd serengeti board.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1080 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-19 02:43:46 +00:00
Myles Watson
539a101e1b This patch changes unsigned [int] to u16 for subsystem IDs. They're in the
hardware and have a specific size.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1069 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-10 19:07:16 +00:00
Myles Watson
72c2e85313 This patch changes all occurrences of pci_dev_set_resources ->
pci_set_resources.  There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
 
Signed-off-by: Myles Watson <mylesgw@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-24 14:06:10 +00:00
Myles Watson
bfa2dc9335 This patch fixes the 8132 so that it can use a 40-bit address space and so
that it uses the correct functions.  Using the device functions on the bridge
was not so good for it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1046 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-19 03:11:52 +00:00
Myles Watson
4e9c6f3669 Correct ops pointers in amd8111 dts.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1041 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 22:24:11 +00:00
Myles Watson
6e882880f2 This patch fixes debug printing.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

Thanks,
Myles


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1038 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 17:53:14 +00:00
Mart Raudsepp
c49f41d946 cs5536: Support NAND flash on other locations than CS0
Modify chipset_flash_setup to support enabling NAND flash on other locations
than CS0, by making enable_ide_nand_flash have a non-boolean meaning where zero
means no NAND (IDE), and 1 through 4 gives the one-based chip select array
location (so 1 means CS0, 2 means CS1, 3 means CS2 and 4 means CS3, as chip
select notation is zero-based).

This loses the code for supporting more than one NAND chip select or different
ones than FLASH_MEM_4K, but these couldn't be supported before anyway, because
that is board specific, but the supporting structure was a static const struct
in generic southbridge specific code.
This support should be instead implemented via the device tree dts files.

Enables NAND on ArtecGroup DBE61 and DBE62 on CS1, as that's where  it is.
The end result is that these mainboards can now boot off of NAND with FILO
without local modifications to the previously existing southbridge specific
static const struct that had no chance of being upstreamed as it would break
all other CS5536 NAND boards that have it on CS0.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@985 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-06 17:52:52 +00:00
Myles Watson
ccba5f1083 This patch removes a warning by making the struct pointer const.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@981 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-05 21:50:25 +00:00
Myles Watson
e7ea68860d Trivial fixes of printk \r\n and white space.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@958 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-28 17:29:07 +00:00
Myles Watson
345f5ac818 Trivial fixes of printk_debug and a comment from v2.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@957 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-28 16:06:28 +00:00
Myles Watson
12f47ecf89 This fixes the 8132 so that it can be included in the build for serengeti.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@956 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-28 02:06:15 +00:00
Marc Jones
ea883f4ad2 Whitespace cleanup on AMD southbridge device_operations structs. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@955 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-27 23:16:17 +00:00
Ronald G. Minnich
cedf16ca69 Marc reviewed the v3 device tree code and we developed the set of
cleanups/fixes.

Fixup device tree code. Add/change methods as needed. 
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-27 20:05:38 +00:00
Uwe Hermann
2174dd2c78 Simplify the PM/PM2 related functions and make them more readable.
Self-acked, as this was acked/committed in v2 already (r3680).

Build-tested with the AMD dbm690t target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@948 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-23 13:09:31 +00:00
Ronald G. Minnich
6dc3ebfb5c Having received no comments on this pro or con, and knowing we have to
have this code, I'm comitting it.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@934 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-16 16:02:12 +00:00
Uwe Hermann
5cd018b2ca Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Build-tested with the AMD dbm690t board.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@922 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-13 21:41:03 +00:00
Carl-Daniel Hailfinger
e3abcbefc2 Replace magic numbers with existing symbolic constants. SB600 is heavily
affected. This mostly targets pci_*_config*() calls.

This is part of my quest to make existing code more readable without
looking up the meaning of magic numbers.

Ron pointed out that this enables better kscope usage.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@913 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-09 22:19:53 +00:00
Ronald G. Minnich
e3517187a0 Fix the sb600 and rs690 code in the same way we just fixed the amd8111.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@911 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-09 15:11:52 +00:00
Ronald G. Minnich
bf6d16032e This gets us to etherboot again, but this time devices are set
up correctly on bus 1 --- i.e., the scan of the 8111 bridge works. It 
even 
tries to find the vga rom to run it, which we did not get before. 

the pci bus map built by coreboot matches simnow. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@910 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-09 14:54:29 +00:00
Ronald G. Minnich
a76e76a6e1 We shouldn't assume the presence of a working HDA codec, so put in
a reasonable timeout of 50usecs (timeout value borrowed from the kernel).
This makes SimNow work, since apparently though the codec is 
present in Simnow, it is non functional.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@904 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-07 00:29:36 +00:00
Ronald G. Minnich
b1dfc9858a This sb600 and rs690 support for a dbm690t that compiles. Stage0 is
23K, too large.    

dbe62 was tested and works i.e. this does no harm.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@893 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-06 17:12:38 +00:00
Myles Watson
fba91167e3 Trivial white space cleanup.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@887 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 20:10:29 +00:00
Ronald G. Minnich
cadd0126aa First cut at moving from v2 to v3.
There are some interesting issues here. The enables for the various 
devices are a global bitmask: 
Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)

But v3 would allow us to not have the bit mask. OTOH, we would end up 
with 3 .dts files for the pcie ports for this enable; good or bad? 
GOOD --> highly custom configuration possible for each port
BAD --> 3 .dts files

Part of the issue is that the link from the dts to the device operations 
structure is done as follows: 
struct device_operations sb600_usb2 = {
	.id = {.type = DEVICE_ID_PCI,
		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
			      .device = PCI_DEVICE_ID_ATI_SB600_USB2}}},

And this structure is named in the .dts for that device_operations:
{
	device_operations = "sb600_usb2";
};

requiring a different dts node for each set of device_operations. 

The device tree compiler generates the code to create these connections 
and puts that code into the the static_tree.c file. 

Having a .dts file for each port gives us a lot of flexibility; but is 
it too inconvenient? This is an unresolved problem; unhandled at present 
for the *6* USB ports for the sb600. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@886 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 15:47:10 +00:00
Peter Stuge
e6a0cc07a7 Fix copypaste errors in the LPC PCI ID and the sata device_ops struct name.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@884 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 04:20:04 +00:00
Peter Stuge
c79c5e1a36 Fix PCI struct name.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@883 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 04:13:54 +00:00
Peter Stuge
84c6bce2c6 Fix device name in ac97audio dts.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@882 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 04:08:15 +00:00
Ronald G. Minnich
d3ae8e7951 Let's add sb600 to the v3 repo this time.
My apologies. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@881 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 03:56:56 +00:00
Ronald G. Minnich
e053a1004c substantial cleanups for k8.
AMP TinyGX still builds, this won't affect other platforms. 

clean up 8111 stage1 code; add function to smbus, 
memreset_setup_amd8111, for the 8111 specific parts of memreset. 

include k8 .h to reduce warnings. Turn some things into functions (romcc
legacy cleanup) and put them in .c files. 

simnow actually successfully gets through a reset cycle now. 

Next is to fix the fidvid code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@868 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-19 18:35:22 +00:00
Ronald G. Minnich
d7ef3c4fd2 EMERGENCY patch for a stupid typo. This code won't compile without these includes.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@864 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:29:02 +00:00
Ronald G. Minnich
5a74d7889b Here is an alternate approach to getting rid of the static in cs5536
smbus.

Set up a global var variable called spd_inited. It is set when spd is 
inited.

For simple cases, nothing is visible to initram main. For complex cases,
initram main can do the work and set this variable.

This compiles and runs on dbe62, which is actually meaningless since 
dbe62
has not smbus, but hey ...

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@863 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 02:19:59 +00:00
Ronald G. Minnich
9cdd8a9d67 This finishes the fix to log2. The computed dram size now matches the
size indicated by byte 31 of SPD. 

Memory is still not working; hanging in dqs training. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@854 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-01 02:44:08 +00:00
Carl-Daniel Hailfinger
27b2fb4f07 Every GeodeLX target already has spd_read_byte in
mainboard/$VENDOR/$BOARD/initram.c. It's pointless to have it in the
southbridge code as well.
Kill it in the southbridge code and use mainboard code only.

Thanks to Segher for rediscovering this bug.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@830 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-27 22:58:04 +00:00
Ronald G. Minnich
8a9d1f2b24 Grow rom space. This now gets a triple fault but I am hoping some smart
person can fix it.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@820 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 19:55:45 +00:00
Ronald G. Minnich
159354e6ba If you get a warning, it's because you SHOULD be getting a warning.
next step is to fix up this:
   LAR     build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 
1
make: exit 2

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 03:27:28 +00:00
Ronald G. Minnich
f28a44eb48 This now compiles (with many warnings but ...) and tries to build a rom
image, and fails: 
  LAR     build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 
1

Next step is to get rid of all warnings that are not #warning. 

Then it is on to simnow. 

Anyone who wants to work on the warnings is most welcome to. 

DBE62 still builds with no problems. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 02:59:05 +00:00
Carl-Daniel Hailfinger
87914c3169 The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@805 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 18:24:53 +00:00
Carl-Daniel Hailfinger
358403335f smbus_delay() performs its own inb(0x80). We can use the generic
udelay() instead which does the same, and achieve better abstraction.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@799 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 10:56:36 +00:00
Carl-Daniel Hailfinger
ff03939b79 CS5536 UART: better depbug prints.
This is the part of the acked patch which was to become r649 but missed
in the check in.
I'm reusing the signoff and ack.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@796 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 00:34:28 +00:00
Carl-Daniel Hailfinger
c407b9e1e0 - Improve VPCI hiding debug message and add doxygen comments.
- Replace a hand-crafted open-coded VPCI hiding sequence.

Build tested on all relevant targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@787 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 20:18:53 +00:00
Carl-Daniel Hailfinger
1b22622323 Change v3 makefile rules to be source-based, part I.
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.

This pepares the way for additional optimizations during compile and
link time.

Build tested and boot tested on Qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 11:15:43 +00:00
Ronald G. Minnich
1dfd5f9321 This gets closer to building serengeti. The next step is to go back and flush out all the
issues in k8 north.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@776 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-16 02:34:51 +00:00