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c49f41d946
Modify chipset_flash_setup to support enabling NAND flash on other locations than CS0, by making enable_ide_nand_flash have a non-boolean meaning where zero means no NAND (IDE), and 1 through 4 gives the one-based chip select array location (so 1 means CS0, 2 means CS1, 3 means CS2 and 4 means CS3, as chip select notation is zero-based). This loses the code for supporting more than one NAND chip select or different ones than FLASH_MEM_4K, but these couldn't be supported before anyway, because that is board specific, but the supporting structure was a static const struct in generic southbridge specific code. This support should be instead implemented via the device tree dts files. Enables NAND on ArtecGroup DBE61 and DBE62 on CS1, as that's where it is. The end result is that these mainboards can now boot off of NAND with FILO without local modifications to the previously existing southbridge specific static const struct that had no chance of being upstreamed as it would break all other CS5536 NAND boards that have it on CS0. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@985 f3766cd6-281f-0410-b1cd-43a5c92072e9 |
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| amd8111 | ||
| amd8132 | ||
| amd8151 | ||
| cs5536 | ||
| rs690 | ||
| sb600 | ||