This needs some extra headers in amdk8/raminit.c that were otherwise
provided by that file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I93fc04d84b412f5db1c80766f28d1f31d8d8fe6a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 3eff00ec76
Original-Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19360
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490681
1. Select CONFIG_{TPM,TPM2} only when MOCK_SECDATA is not selected.
2. Provide tlcl_lib_init for mock TPM case.
BUG=b:37682566
TEST=Verified that when mock TPM is used, CONFIG_TPM is not set
anymore in coreboot config.
Change-Id: Ib704fe98cab5d6f13b5b7ea75d0ba242ed7e386a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 00f360e3f1
Original-Change-Id: If3bdd1528e153b164e9d62ee9cbcc4c3666b8b66
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19456
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490680
Create Intel Common ITSS code. This code currently only contains
the code for Interrupt initialization required in Bootblock phase.
More code will get added up in the subsequent phases.
BUG=none
BRANCH=none
TEST=none
Change-Id: I235ad1f657752906425ef739c69ec0fc06df7140
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: fcab4156c8
Original-Change-Id: I133294188eb5d1312caeafcb621fb650a7fab371
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19125
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490677
The SRS bit which is supposed to indicate reset button press
is non-functional. If it did work the system reset event it
was associated with is overly specific. Therefore, use the
warm reset status bit.
BUG=b:37687843
Change-Id: I60636f2ec24e4255a718fa3c087a55006411def2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: f39692ee3e
Original-Change-Id: I34dd09c03d2bca72da9a5cdf23121e0d0e621fa6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19484
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490676
It's come to attention that apollolake doesn't support a full retrain
on warm reset. Therefore force a cold reset when a full retrain is
requested in the non-S5 path.
BUG=b:37687843
Change-Id: Icea92953ccdb1c3233d1b5df5620b3f338eb0f46
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 9c86aafe5a
Original-Change-Id: If9a3de1fa8760e7bb2f06eef93a0deb9dbd3f047
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19483
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490675
Update default ODT config to have correct CA ODT settings as the
current defaults are incorrect for all the current apollolake designs.
All the current designs pull both A and B channels' LPDDR4 modules' ODT
pins to 1.1V. Therefore, the correct impedance setting needs to be
applied.
In order for the settings to take effect one needs to clear the
memory training cache in deployed systems. Trigger this by bumping
the memory setting version for the SoC.
If needed in the future support for allowing the override of this
setting from the mainboard should be straight forward. It's just not
necessary at this time.
BUG=b:37687843
TEST=BAT test, warm, reboot, S3 cycle test
Change-Id: Ie359847db7391798b2dce5301addecb3d95c88cc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: a3d13fbd69
Original-Change-Id: I9a2f7636b46492a9d08472a0752cdf1f86a72e15
Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19397
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/490674
On Chrome OS systems a memory setting change is needed to be deployed
without updating the FSP blob proper. Under such conditions one needs
to trigger retrain of the memory. For ease of use provide an option,
FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC
and mainboard memory setting version number into the FSP version
passed to the platform. The lower 8 bits of the FSP version are the
build number which in practice is normally 0. Use those 8 bits to
include the SoC and mainboard memory settings version. When FSP,
SoC, or mainboard memory setting number is bumped a retrain will be
triggered.
BUG=b:37687843
Change-Id: Ia0298efc1cb40716f808fcd2779a0d56ebec800a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: a3cecb2e71
Original-Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19452
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490673
Ironically enough, libsanitizer is notorious for creating "uninitialized
variable" warnings with different compiler versions than the one it's
shipping with.
Since we don't need it for building the real compiler, just skip it.
Fixes building our compilers using the gnat-gpl 2014 compilers.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib867e7f7bd8709659f7b49d76ba441904e15db14
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97a9df4f77
Original-Change-Id: I2130dfdf3eaf07d77cd70777419fc0ae4642b843
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19478
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/490083
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Add basic SMM support for Broadwell-DE SoC.
The code is mainly based on the SMM implementation of Broadwell with a
few differences:
- EMRR is now called PRMRR and the UNCORE part of it is not available
- SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space
- currently only SERIRQ-SMI has a handler
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic135fe932daed0cb63690d5675786933715c45a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97c0979bef
Original-Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19145
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490082
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
On Apollo Lake it was discovered that our current FADT implementation is
valid for ACPI version 3.0 but misses fields for ACPI version 5.0. We
run into booting issues with Windows 10 using version 5 in the FADT
header. In commit 2b8552f49bc3a7d0290f96a84b573669de396011
(intel/apollolake: Switch FADT to ACPI version 3.0) we go back to
version 3 for Apollo Lake. Skylake is now the last platform that uses
version 5 in FADT header.
BUG=none
BRANCH=none
TEST=none
Change-Id: I70041118196641bb6cbf90cd8d16723bdca9be59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00d250e228
Original-Change-Id: I2d0367fae5321dee4ccac417b7f99466f8973577
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19453
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490081
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The current implementation of the FADT structure is only ACPI 3.0 compliant.
Setting the version to ACPI 5.0 results in a corrupt FADT. Linux seems
to be able to deal with it but Windows 10 hangs in a really early stage
without any notification to the user.
If ACPI 5.0 is mandatory, the FADT structure needs to be adjusted to
match the specification. Therefore the members sleep_ctl and sleep_stat
needs to be added to FADT structure.
BUG=none
BRANCH=none
TEST=none
Change-Id: I009e765f7aabfc984af95e82c5cb632b81b54532
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27e6042bb7
Original-Change-Id: I51c7a7a84d10283f5c2a8a2c57257d53bbdee7ed
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19146
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490080
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Move the images around in the image stitching. This addresses
an issue found with PSP firmware loading on the Google Kahlee
mainboard.
Note firmware1 must come before firmware2 in the image or
the PSP will not allow APU to execute.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2d6d3cd1093c5dbe9fe57ce1ed03d30f8ef5be06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d81250cebc
Original-Change-Id: I85963fa93d6efd707cedfbc04b92d302ad5de3b1
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19170
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490078
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The new touchpad firmware uses i2c-hid instead of custom reporting
protocol. The touchpad also exposed another slave address (0x1e) for
kernel to communicate with the touchpad EC.
BUG=none
BRANCH=none
TEST=none
Change-Id: I717e1e1b5b739bef34c697e4f7ab4cb1b7593862
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 267e4a5824
Original-Change-Id: Iecaf14f7b8aed836120569e9ade9c3115bc00264
Original-Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Original-Reviewed-on: https://review.coreboot.org/19461
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490077
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Add a check for vboot when locating the binaryPI image.
There is currently an ordering problem using cbmem to locate the
image when vboot is present. Vboot inserts its locator into the
search process so that memory can be checked before flash is queried.
For the earliest calls using the wrapper, DRAM has not been set up
and cbmem not initialized in romstage. This change prevents an
endless loop when vboot searches cbmem.
This change has another side effect. When vboot is in effect, the
change forces the RO binaryPI to be used even when on either of the
RW paths. There is currently no ability to relocate the XIP image
for use in a RW region.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474)
BUG=none
BRANCH=none
TEST=none
Change-Id: If30b23954f97cc4565ff81b55ee3a9e4145be379
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca3815b4c5
Original-Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
AMD VBIOS option ROMs often modify themselves during initialization.
Check for the presence of a VBIOS at 0xc0000 before populating the
VFCT table. If a matching ROM is found, use it for the source of
the copy.
Tested on Gardenia (Stoney) variant by observing amdgpu driver's
dmesg output.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2c5d6487d22d551e07dbc0fd0da7d7e75a134c96
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f978cfd1a
Original-Change-Id: I5be7e1562bde51800c5b0e704c79812d85bcf362
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19383
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490075
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
We need to rewrite libtool's files (foo.la) a couple of times so it
knows where to look
(while still whining that $DESTDIR$TARGET != $TARGET. well, duh.)
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib444c60924e48f5adcefeecccdb0a24250075b12
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 790aab6c77
Original-Change-Id: I54cafd47c76d855222ba905b5eb4533a23bdfd34
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19463
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/490074
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
In order for PD charge events to properly notify the OS when a charger is
attached we need to enable the PD MCU device and event source from the EC.
Without this change the charging still happens, but the OS does not notice
and update the charge state icon in the Chrome OS UI.
BUG=b:35586577
BRANCH=none
TEST=On a poppy board that has the VBUS rework applied, plug in a charger to
either port and see charge status updated to indicate charging in the
power_supply_info tool and the Chrome OS UI.
Change-Id: I07ca5d7383e5e6b014a6b35c2b7c5ba6edd1234e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb368db2a4
Original-Change-Id: I59dcfc1cb5d11841f56cac7f4ffe461c2f9ec52a
Original-Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19441
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/490073
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
If the mainboard supports VBNV, call init_vbnv_cmos() instead of
the normal init_cmos(). The VBNV version does some VBNV pre
and post setup around the normal init_cmos().
BUG=none
BRANCH=none
TEST=none
Change-Id: I6754b2789175ea9bd61235bcecdf1ffdc7fccb42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 956a58e4fe
Original-Change-Id: I34b02409019b945cd68c830e006e99338643f29c
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19399
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490072
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.
Since the LPC function claims the resources for IOAPIC, ROM and
low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI
configuration will not overlap those regions and does not hide
the resources mentioned in the original comment.
The bridge was disable in the following commit [1]
commit a8e1168064
Author: Stefan Reinauer <stepan@coresystems.de>
Date: Wed Mar 11 14:54:18 2009 +0000
This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:
but unfortunately it was not noted which system this caused
problems with.
[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6
BUG=none
BRANCH=none
TEST=none
Change-Id: I6020ee2d6fbd01dc6a0a5f9d0cedb97056d0cfb2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a2b7bd859a
Original-Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/2706
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/490071
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
This reverts commit e7394ca903.
Configuration register for ACPI PM base address is initially configured
inside the PI blob. Therefore, the value of HUDSON_ACPI_IO_BASE needs
to be the same as DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS used in the build
of binaryPI blob.
BUG=none
BRANCH=none
TEST=none
Change-Id: I02857c5299493d0723c86c46cd5a3a46b46973f5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 771e8c114f
Original-Change-Id: I36700e49e21cc675e8e22b06efffb40e9c1e4236
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19454
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/490067
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Replace ram_check with quick_ram_check, because ram_check is slow and
is destructive for dram content.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibb484e1894fa86c1f47a03a61ff4d0ace1452838
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58ab3bed82
Original-Change-Id: I5fb1bfe711549aabb6e597bda22848988a7e9cbe
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19416
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/488283
MMA blobs are SOC specific (not board). So far MMA
is supported by big cores (SKL and KBL).
BUG=none
BRANCH=none
TEST=none
Change-Id: I511652c7f5492f52ff2446bfc214d92ed79c1e7c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebb7994263
Original-Change-Id: I922789a2a12d55360624dd6de15ab9f0bb5f0acf
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19260
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/488281
Add a function to send the TPM decode to the SPI interface.
Enables use of SPI TPMs on Hudson mainboards.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7ae140e18c3e0a3c43e72dcb899ee8bd68beb945
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6fcaaef614
Original-Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19402
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/488060
Change spaces to tabs and do general whitespace cleanup.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia4732dca1545b784de5c839e074eb9122ff2b7e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c1f32336e6
Original-Change-Id: I4a4ecd42f91c9c6015a4f065b7386b17523ac6d9
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19401
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/488059
Move the ACPI IO registers from 0x800 to 0x600 to avoid the
IO space required by the Google EC, also at 0x800.
This shouldn't have any conflicts on other AMD systems.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae32c2450667da500771d9aada2e121da0c467a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7394ca903
Original-Change-Id: Iac7388c15e899277fd506fb37965164488358335
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19171
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488058
Add a function to enable LPC IO decode AKA WideIO.
This can enable up to 3 regions, which may be 512 or 16
bytes wide.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id7b09a5df91744b8a0cdcf86a3d80d28880db3d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f962aa52d6
Original-Change-Id: I2bed3a99180188101e00b4431d634227e488cbda
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19160
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488057
It turns out that there are quite a few other projects that can access
the CBMEM console by now. If we ever want to make another structural or
behavioral change to it, we need to know where these implementations are
so we can make sure they're all getting updated. Let's try to build a
comprehensive list in the file that should be the source of truth for
all (coreboot's own implementation).
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae97ac8306e640fde6bd2300f62b7fcaf960eea0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a915cea289
Original-Change-Id: Ia3d6a87230f5bfdde9d812bc7154e22880c1377a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19439
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/488056
Add a basic GPIO get function.
Note that GPIO set, ACPI/GPE, and other features should come
in future commits. Future changes to be modeled on the other soc/
gpio functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: I816c7a6f50d25ef70ae7c87a2642d746d09b6f6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dae95f0dfe
Original-Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19159
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488055
The silicon specific mainboard_romstage_entry() in amd/cpu/car.h,
which is used by all AMD silicon car code, caused a conflict.
Move the silicon specific defines to silicon header files. Also,
no longer include car.h in the romstage file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1b0d54a7697be3c985693020078200705f08d1b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4aad421e81
Original-Change-Id: Icfc759c4c93c8dfff76f5ef9a1a985dd704cfe94
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18769
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488054
These files are actually indentical, but unfortunately, the formatting
was changed without caring for the already present files. Fix that. Use
the license formatting where less lines are used.
The next step is to put that in a common location.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7b8ec432871845f5ae16f43508f8e922ada35e16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d06c51895e
Original-Change-Id: Iecb263b9d321a33e64988b315220893df2e0045c
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/19423
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/488053
According to the comment above the default should dump the EC ram,
though is never reached since the variable 'write_addr' is not 0, but
initialized at -1.
Also removes brackets around one line statement below if to make
checkpatch.pl happy.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6e055b5ad1c2bbd62ac450a9c38267fd92fc884e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 878c2de41b
Original-Change-Id: I390996b253f2f20682cd9ab2d4f560de6eccfc57
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19152
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/488052
When setting output to verbose, it incorrectly reports that it times
out on every command.
TESTED on Thinkpad X60.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibff3a5d8b073ab5fb40d5fbfda2137a725574e02
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2873a4aea4
Original-Change-Id: I24f05f0c165462d5ba2604c7e2fe139400683275
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19151
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/488051
Utilize the postcar stage for tearing down CAR and initializing
the MTRRs once ram is up. This flow is consistent with apollolake
and allows CAR_GLOBAL variables to be directly accessed and no
need for migrating CAR_GLOBAL variables as romstage doesn't
run with and without CAR being available.
BUG=none
BRANCH=none
TEST=none
Change-Id: I78458fefac96d714eeacc3832a2c4818d2fcd016
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 79f0741f81
Original-Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19335
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488049
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0409e8e9d6a203254a9f9b749de5cab70dfc842
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4d7abc0d4
Original-Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19333
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488047
The console log level variable doesn't really rely on ROMSTAGE_CONST
proper. Instead, the mutability of the variable is based on the current
implementation of ROMSTAGE_CONST (__PRE_RAM__). As such directly
use that logic for the code. In addition, refactor the code to let
the compiler and linker optimize out accesses instead of using
the pre-processor.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie38d062b92b9bcd7bf7faf88a9495c52c0d5488d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4003950881
Original-Change-Id: I44bcc409266ef52b9be29f75efde73a6707a53f4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/488046
The ramstage-c-ccopts variable needs to be double dereferenced
for the cbfs-files-processor-struct handler so all the ccopts
are included since the ramstage-c-ccopts is fully constructed
later by another function. Without this not all the flags
are present on the command line.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic3d0b9f7ddf2cd0d3b542bd35a2d7e209a77c364
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42bcd13c75
Original-Change-Id: I5425b3c1f23d767c61f654dd287584403f85d719
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19380
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/488045
Delete the write to PM register 0xee. This register is not
listed in the current BKDG and S4 is not currently supported
on this APU.
NDA document #47517 "A55/.../A85X fusion Controller Hub Register
Reference Guide" provides some clues on the intent of this write.
This register has always been observed to power on with a value
of 0x08 so the write has no effect.
This should be revisited again when SMI and PSP fully implement
the support required for S3.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7c01148c21a07b51848f59e85161cb30450fa7a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e438af995
Original-Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18494
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486780
