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Author SHA1 Message Date
Marc Jones
a794edb17b Setup the MTRRs in stage1 so that memory and cache are available throughout 
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2009-02-10 22:40:10 +00:00
Myles Watson
dbc272b26e This patch adds two k8 devices from v2 to v3 (apic and mcf3.) 
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1063 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-12-03 15:38:42 +00:00
Ronald G. Minnich
979bdb5ed0 Add functions to print routes. 
I am totally convinced these are right. I am going on travel for a week 
and want these in your hands. 

Carl-Daniel as acked these, but for lack of time to get firefox going 
right now, 

Current serengeti output
DRAM(40)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(48)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(50)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(58)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(60)00000000-00ffffff, ->(4), , , No interleave, 0
DRAM(68)00000000-00ffffff, ->(0), R, W, 8 nodes, 0
DRAM(70)00000000-00ffffff, ->(0), , , No interleave, 0
DRAM(78)00000000-00ffffff, ->(0), , , No interleave, 0
MMIO(80)01a00000-1100ffff, ->(0,2), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(88)75060000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(90)51040000-3f00ffff, ->(0,0), , , CPU disable 1, Lock 0, Non 
posted 0
MMIO(98)00000000-0000ffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non 
posted 0
MMIO(a0)01c00000-1100ffff, ->(0,1), , , CPU disable 0, Lock 0, Non 
posted 1
MMIO(a8)75000000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(b0)51040000-0000ffff, ->(0,0), , , CPU disable 1, Lock 0, Non 
posted 0
MMIO(b8)00000000-0000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non 
posted 0
PCIIO(c0)00001010-00003110, ->(0,1), , ,VGA 0 ISA 0
PCIIO(c8)00000750-00000000, ->(2,0), , ,VGA 0 ISA 1
PCIIO(d0)00002510-00000000, ->(0,0), , ,VGA 1 ISA 0
PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
CONFIG(e0)00000000-00000000 ->(0,0),  CE 0
CONFIG(e4)00000000-00000000 ->(0,0),  CE 0
CONFIG(e8)00000000-00000000 ->(0,0),  CE 0
CONFIG(ec)00000000-00000000 ->(0,0),  CE 0

Either the DRAM output is wrong or there is a real problem with our 
DRAM programming. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@941 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-10-21 03:20:05 +00:00
Ronald G. Minnich
e4e80a7ee0 add new socket type (trivial) 
Signed-off-by: Ronald G. Minnich <rminnch@gmail.com>
Acked-by: Ronald G. Minnich <rminnch@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@880 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-10-02 16:07:10 +00:00
Ronald G. Minnich
be03d189db Finally, after two years, put in real code for stop_ap(). Code has to be 
moved to stage1 ROM code. Make the struct for nodeid/coreid generic to 
x86. Create the functions for existing architectures are a model for 
future architectures (VIA coming soon we hope). 

Move includes so that things build correctly now. 

This is actually a small patch that impacted a number of files due to 
include order changes. This is build and boot tested on simnow and 
build tested on geode. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@872 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-09-29 14:58:56 +00:00
Ronald G. Minnich
e053a1004c substantial cleanups for k8. 
AMP TinyGX still builds, this won't affect other platforms. 

clean up 8111 stage1 code; add function to smbus, 
memreset_setup_amd8111, for the 8111 specific parts of memreset. 

include k8 .h to reduce warnings. Turn some things into functions (romcc
legacy cleanup) and put them in .c files. 

simnow actually successfully gets through a reset cycle now. 

Next is to fix the fidvid code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@868 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-09-19 18:35:22 +00:00
Ronald G. Minnich
ff2ddcb313 This gets us back to a compiling k8 target. 
This code has been tested on dbe62, and builds for qemu as well. 

the next step is testing on simnow. 

k8.h: add more prototypes and some required inline functions. 
cpu.h: same
serengeti: expand defines in mainboard.h, though we need a better 
mechanism; continue to fix initram.c, add new support files to Makefile
lib/console.c: include globalvars.h
lib/lar.c: Provide more informative print as the lar is scanned.
k8 north: needed reset_test.c from v2, fixes to raminit.c
arch/x86
Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory
	used for coreboot. 
init_cpus.c: functions to start up CPUs
stage1_mtrr.c: bring over early mtrr support from v2.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-30 03:35:40 +00:00
Ronald G. Minnich
f365719d09 This is closer! There are < 10 functions to be worked out, so most of 
what you get are warnings. 

There is lots of room for improvement as we move to all CAR 
code, but that will take time. 

I hope to get this to really compile over the weekend. 

At the same time, if anybody wants to take a crack at it, your efforts
are welcome.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@843 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-29 04:33:56 +00:00
Ronald G. Minnich
96e0fd18bf Fixes to make k8 and others work. 
We need the sys_info struct in the global variables struct for 
cache as ram on k8. The sys_info struct is generally very useful
so it makes sense to start accomodating it.  

This patch adds an (empty for now) sys_info struct for geode. 
It add sys_info to the global variables struct. 

It removes global variables from console.h to a new file, 
globalvars.h. Very little code needs to include this file. 

This patch is tested on the dbe62 and simnow with no problems.

k8 compilation is now broken but I'm working on it. I'm going through
the eyeballs-bleed code on k8 startup to document it and with any luck 
we'll have more functionality by the end of today. But it's hard ...

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@828 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-27 22:43:18 +00:00
Ronald G. Minnich
62f8ea8e9b This set of changes gets us much farther, in fact, we get into initram. 
This means that basic resource maps are working, initial hypertransport 
setup is working, the amd8111 ISA device is working, config space is 
working for all the parts, we can grow the FLASH part address space to 
more than 64k, and in general we're having a good time. 

Here is the output:
coreboot-3.0.824 Tue Aug 26 22:18:21 PDT 2008 starting... 
(console_loglevel=8)
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: normal/stage2/segment0@0xfff866f0, size 1
LAR: normal/stage2/segment1@0xfff86750, size 18542
LAR: normal/stage2/segment2@0xfff8b010, size 559
LAR: normal/payload/segment0@0xfff8b290, size 18142
LAR: bootblock@0xffff7fc0, size 32768
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: CHECK normal/initram/segment0 @ 0xfff80740
start 0xfff80790 len 24404 reallen 24404 compression 0 entry 0x00000004 
loadaddress 0x00000000
Entry point is 0xfff80794
Hi there from stage1
stage1 returns
run_file returns with 0

Goal for tomorrow is to get initram done. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@826 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-27 05:30:50 +00:00
Ronald G. Minnich
784450567f This now compiles and has a simple error on build to stage2. 
Geode still builds fine. 

include/lib.h includes a new function, cycles(), which is a u64 and 
architecture-defined. (Thanks, Plan 9, for a sensible idea). 

All rdtsc removed in favor of cycles()

All other changes are k8 specific. None of these changes adversely 
impact existing platforms AFAICT. 

Goal is that by 31/8/8, we're testing on simnow. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@807 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-23 16:51:00 +00:00
Ronald G. Minnich
4110e67004 Add ddr2 defines. 
Continue to upgrade northbridge for k8. 

Add a new standard include (which is optional on some chipsets), 
mainboard.h, which will define important mainboard constants that
1. do not belong in dts
2. do not belong in Kconfig
3. are so tightly tied down to the mainboard they should probably not be 
visible, i.e. the value of the variable is defined by artwork on the 
mainboard, such as the socket type. 

This file resolves the long-standing question of where certain 
mainboard-dependent, compile-time control variables belong. 
We've not resolved this issue in two years so here's how 
we're going to do it. The first use of this is in the definition of 
CPU_SOCKET_TYPE, needed by the northbridge code. 

These changes do not affect existing Geode builds (tested on DBE62). 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@792 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-21 16:04:41 +00:00
Ronald G. Minnich
44d1585458 per discussion w/AMD, remove all conditionals based on REV_F. 
It's all REV_F now and we're wasting time pretending otherwise. This 
change simplifies the code and will continue to simplify the code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@788 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-18 20:31:34 +00:00
Ronald G. Minnich
7102949d76 We're much closer. 
Added a stepping enum to k8.h. This will allow us to do things like this:
if (cpu_stepping(node) < E0)

and so on instead of is_cpu_pre_e0_in_bsp or whatever it is. 

Added and fixed Kconfig variables. 

Broke out northbridge by function, so we can see what goes with what. 

This tree still builds a working DBE62 coreboot that boots a kernel; no harm done to existing ports. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@781 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-17 22:18:09 +00:00
Ronald G. Minnich
7e78ce492a Make some things (die, mem*, resourcemap code, option code) SHARED. 
The option code is tricky as it is used by standalone code. If you 
include that file and you are standalone, you now have to define 
STANDALONE (is there a better way?)
Change the cpuid to be a 24-byte string instead of 3 u32s.
Make the CPUID usage PIC-safe by not using %ebx.

Test building on two different geodes, tested to boot on dbe62

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@750 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-12 03:39:39 +00:00
Ronald G. Minnich
120f4203a9 Add needed defines for k8 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@732 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-10 22:02:15 +00:00
Ronald G. Minnich
da9286b479 State of the tree for K8 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-05 02:48:54 +00:00
Ronald G. Minnich
30c0db46ed We're getting closer. It has been pointed out that this code is not pretty. I agree. Get 
it working, then we'll get it pretty. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-03 22:42:01 +00:00
Peter Stuge
41242a63c3 v3: k8/m57sli wip1 
This is not nearly complete, but just the current state of my tree.

k8/raminit.c does not compile at all. Lots of fixes are still needed to bring
it working into v3. I've gone through about 1/8 of the file, it errors out on
line 576 now.

The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.

Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually see the first v3 k8 build. :)

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@713 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-02 03:34:05 +00:00
Ronald G. Minnich
526a61a6e5 rename per IRC 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@706 f3766cd6-281f-0410-b1cd-43a5c92072e9
 2008-08-01 18:00:54 +00:00