This patch adds two k8 devices from v2 to v3 (apic and mcf3.)

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1063 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2008-12-03 15:38:42 +00:00
parent eb09a75c49
commit dbc272b26e
7 changed files with 261 additions and 12 deletions

View file

@ -580,7 +580,7 @@ enum {
/* note: we'd like to have this sysinfo common to all K8, there's no need to
* have one different kind per different kind of k8 at this point.
*/
//#include "raminit.h"
#include "raminit.h"
struct dimm_size {
u8 per_rank; // it is rows + col + bank_lines + data lines */
@ -608,14 +608,6 @@ struct mem_info { // pernode
u8 rsv[3];
} __attribute__((packed));
struct mem_controller {
unsigned node_id;
/* NOTE: these are in "BDF" format -- i.e. bus in upper 16, devfn in upper 8 of lower 16 */
u32 f0, f1, f2, f3;
u32 channel0[DIMM_SOCKETS];
u32 channel1[DIMM_SOCKETS];
};
struct link_pair_st {
u32 udev;
u32 upos;
@ -685,8 +677,9 @@ unsigned int get_core_count(void);
void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
const u16 *spd_addr);
int lapic_remote_read(int apicid, int reg, unsigned int *pvalue);
void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id,
/*void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id,
const char *str);
*/
unsigned int wait_cpu_state(unsigned apicid, unsigned state);
void set_apicid_cpuid_lo(void);
/* fidvid.c */

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@ -21,8 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define DIMM_SOCKETS 4
#define NODE_NUMS 16
#define CPU_SOCKET_TYPE SOCKET_AM2
#define MEM_TRAIN_SEQ 0 /* for now */
#define HW_MEM_HOLE_SIZE_AUTO_INC 0

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@ -27,6 +27,8 @@ STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/get_sblk_pci1234.c \
$(src)/northbridge/amd/k8/cpu.c \
$(src)/northbridge/amd/k8/domain.c \
$(src)/northbridge/amd/k8/pci.c \
$(src)/northbridge/amd/k8/mcf3.c \
$(src)/northbridge/amd/k8/apic.c \
$(src)/northbridge/amd/k8/util.c
endif

24
northbridge/amd/k8/apic Normal file
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@ -0,0 +1,24 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{
/* Miscellaneous Control Function 3 for Athlon/Opteron. */
device_operations = "k8_apic_ops";
};

26
northbridge/amd/k8/apic.c Normal file
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@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
struct device_operations k8_apic_ops = {
.id = {.type = DEVICE_ID_APIC},
.ops_pci = 0,
};

24
northbridge/amd/k8/mcf3 Normal file
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@ -0,0 +1,24 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{
/* Miscellaneous Control Function 3 for Athlon/Opteron. */
device_operations = "mcf3_ops";
};

182
northbridge/amd/k8/mcf3.c Normal file
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@ -0,0 +1,182 @@
/* Turn off machine check triggers when reading
* pci space where there are no devices.
* This is necessary when scaning the bus for
* devices which is done by the kernel
*
* written in 2003 by Eric Biederman
*
* - Athlon64 workarounds by Stefan Reinauer
* - "reset once" logic by Yinghai Lu
*/
#include <console.h>
#include <lib.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#warning Broken hard_reset
//#include <part/hard_reset.h>
#include <mc146818rtc.h>
#include <amd/k8/k8.h>
#warning Make AGP_APERTURE_SIZE a CONFIG variable
#define AGP_APERTURE_SIZE 0x4000000 //64M
/**
* @brief Read resources for AGP aperture
*
* @param
*
* There is only one AGP aperture resource needed. The resoruce is added to
* the northbridge of BSP.
*
* The same trick can be used to augment legacy VGA resources which can
* be detected by the generic pci resource allocator for VGA devices.
* BAD: it is more tricky than I think, the resource allocation code is
* implemented in a way to NOT DOING legacy VGA resource allcation on
* purpose :-(.
*/
static void mcf3_read_resources(struct device *dev)
{
struct resource *resource;
unsigned char iommu;
/* Read the generic PCI resources */
pci_dev_read_resources(dev);
/* If we are not the first processor don't allocate the GART aperture */
if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
return;
}
iommu = 1;
get_option(&iommu, "iommu");
if (iommu) {
/* Add a GART aperture resource */
resource = new_resource(dev, 0x94);
resource->size = iommu ? AGP_APERTURE_SIZE : 1;
resource->align = log2f(resource->size);
resource->gran = log2f(resource->size);
resource->limit = 0xffffffff; /* 4G */
resource->flags = IORESOURCE_MEM;
}
}
static void set_agp_aperture(struct device *dev)
{
struct resource *resource;
resource = probe_resource(dev, 0x94);
if (resource) {
struct device *pdev;
struct device_id id;
u32 gart_base, gart_acr;
/* Remember this resource has been stored */
resource->flags |= IORESOURCE_STORED;
/* Find the size of the GART aperture */
gart_acr = (0 << 6) | (0 << 5) | (0 << 4) |
((resource->gran - 25) << 1) | (0 << 0);
/* Get the base address */
gart_base = ((resource->base) >> 25) & 0x00007fff;
/* Update the other northbriges */
pdev = NULL;
id.type = DEVICE_ID_PCI;
id.pci.vendor = PCI_VENDOR_ID_AMD;
id.pci.device = 0x1103;
while ((pdev = dev_find_device(&id, pdev))) {
/* Store the GART size but don't enable it */
pci_write_config32(pdev, 0x90, gart_acr);
/* Store the GART base address */
pci_write_config32(pdev, 0x94, gart_base);
/* Don't set the GART Table base address */
pci_write_config32(pdev, 0x98, 0);
/* Report the resource has been stored... */
report_resource_stored(pdev, resource, " <gart>");
}
}
}
static void mcf3_set_resources(struct device *dev)
{
printk(BIOS_DEBUG, "%s...\n", __func__);
/* Set the GART aperture */
set_agp_aperture(dev);
/* Set the generic PCI resources */
pci_set_resources(dev);
}
static void misc_control_init(struct device *dev)
{
u32 cmd, cmd_ref;
int needs_reset;
struct device *f0_dev;
printk(BIOS_DEBUG, "NB: Function 3 Misc Control..\n");
needs_reset = 0;
/* Disable Machine checks from Invalid Locations.
* This is needed for PC backwards compatibility.
*/
cmd = pci_read_config32(dev, 0x44);
cmd |= (1 << 6) | (1 << 25);
pci_write_config32(dev, 0x44, cmd);
/* Optimize the Link read pointers */
f0_dev = dev_find_slot(0, dev->path.pci.devfn - 3);
if (f0_dev) {
int link;
cmd_ref = cmd = pci_read_config32(dev, 0xdc);
for (link = 0; link < 3; link++) {
u32 link_type;
unsigned reg;
/* This works on an Athlon64 because unimplemented
* links return 0.
*/
reg = 0x98 + (link * 0x20);
link_type = pci_read_config32(f0_dev, reg);
/* Only handle coherent links here please. */
if ((link_type &
(LinkConnected | InitComplete | NonCoherent))
== (LinkConnected | InitComplete)) {
cmd &= ~(0xff << (link * 8));
/* FIXME this assumes the device on the other
* side is an AMD device.
*/
cmd |= 0x25 << (link * 8);
}
}
if (cmd != cmd_ref) {
pci_write_config32(dev, 0xdc, cmd);
needs_reset = 1;
}
} else {
printk(BIOS_ERR, "Missing f0 device!\n");
}
if (needs_reset) {
printk(BIOS_DEBUG, "Not resetting cpu, but it's needed.\n");
//hard_reset();
}
printk(BIOS_DEBUG, "done.\n");
}
struct device_operations mcf3_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = 0x1103}}},
.phase3_scan = 0,
.phase4_read_resources = mcf3_read_resources,
.phase4_set_resources = mcf3_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = misc_control_init,
.ops_pci = 0,
};