mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
This patch adds two k8 devices from v2 to v3 (apic and mcf3.)
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1063 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson
parent
eb09a75c49
commit
dbc272b26e
7 changed files with 261 additions and 12 deletions
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@ -580,7 +580,7 @@ enum {
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/* note: we'd like to have this sysinfo common to all K8, there's no need to
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* have one different kind per different kind of k8 at this point.
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*/
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//#include "raminit.h"
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#include "raminit.h"
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struct dimm_size {
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u8 per_rank; // it is rows + col + bank_lines + data lines */
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@ -608,14 +608,6 @@ struct mem_info { // pernode
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u8 rsv[3];
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} __attribute__((packed));
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struct mem_controller {
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unsigned node_id;
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/* NOTE: these are in "BDF" format -- i.e. bus in upper 16, devfn in upper 8 of lower 16 */
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u32 f0, f1, f2, f3;
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u32 channel0[DIMM_SOCKETS];
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u32 channel1[DIMM_SOCKETS];
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};
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struct link_pair_st {
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u32 udev;
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u32 upos;
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@ -685,8 +677,9 @@ unsigned int get_core_count(void);
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void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
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const u16 *spd_addr);
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int lapic_remote_read(int apicid, int reg, unsigned int *pvalue);
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void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id,
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/*void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id,
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const char *str);
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*/
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unsigned int wait_cpu_state(unsigned apicid, unsigned state);
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void set_apicid_cpuid_lo(void);
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/* fidvid.c */
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@ -21,8 +21,6 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define DIMM_SOCKETS 4
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#define NODE_NUMS 16
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#define CPU_SOCKET_TYPE SOCKET_AM2
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#define MEM_TRAIN_SEQ 0 /* for now */
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#define HW_MEM_HOLE_SIZE_AUTO_INC 0
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@ -27,6 +27,8 @@ STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/get_sblk_pci1234.c \
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$(src)/northbridge/amd/k8/cpu.c \
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$(src)/northbridge/amd/k8/domain.c \
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$(src)/northbridge/amd/k8/pci.c \
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$(src)/northbridge/amd/k8/mcf3.c \
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$(src)/northbridge/amd/k8/apic.c \
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$(src)/northbridge/amd/k8/util.c
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endif
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24
northbridge/amd/k8/apic
Normal file
24
northbridge/amd/k8/apic
Normal file
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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{
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/* Miscellaneous Control Function 3 for Athlon/Opteron. */
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device_operations = "k8_apic_ops";
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};
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26
northbridge/amd/k8/apic.c
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26
northbridge/amd/k8/apic.c
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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struct device_operations k8_apic_ops = {
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.id = {.type = DEVICE_ID_APIC},
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.ops_pci = 0,
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};
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24
northbridge/amd/k8/mcf3
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24
northbridge/amd/k8/mcf3
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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{
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/* Miscellaneous Control Function 3 for Athlon/Opteron. */
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device_operations = "mcf3_ops";
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};
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182
northbridge/amd/k8/mcf3.c
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182
northbridge/amd/k8/mcf3.c
Normal file
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@ -0,0 +1,182 @@
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/* Turn off machine check triggers when reading
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* pci space where there are no devices.
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* This is necessary when scaning the bus for
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* devices which is done by the kernel
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*
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* written in 2003 by Eric Biederman
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*
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* - Athlon64 workarounds by Stefan Reinauer
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* - "reset once" logic by Yinghai Lu
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*/
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#include <console.h>
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#include <lib.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#warning Broken hard_reset
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//#include <part/hard_reset.h>
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#include <mc146818rtc.h>
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#include <amd/k8/k8.h>
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#warning Make AGP_APERTURE_SIZE a CONFIG variable
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#define AGP_APERTURE_SIZE 0x4000000 //64M
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/**
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* @brief Read resources for AGP aperture
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*
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* @param
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*
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* There is only one AGP aperture resource needed. The resoruce is added to
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* the northbridge of BSP.
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*
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* The same trick can be used to augment legacy VGA resources which can
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* be detected by the generic pci resource allocator for VGA devices.
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* BAD: it is more tricky than I think, the resource allocation code is
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* implemented in a way to NOT DOING legacy VGA resource allcation on
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* purpose :-(.
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*/
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static void mcf3_read_resources(struct device *dev)
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{
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struct resource *resource;
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unsigned char iommu;
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/* Read the generic PCI resources */
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pci_dev_read_resources(dev);
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/* If we are not the first processor don't allocate the GART aperture */
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if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
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return;
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}
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iommu = 1;
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get_option(&iommu, "iommu");
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if (iommu) {
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/* Add a GART aperture resource */
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resource = new_resource(dev, 0x94);
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resource->size = iommu ? AGP_APERTURE_SIZE : 1;
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resource->align = log2f(resource->size);
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resource->gran = log2f(resource->size);
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resource->limit = 0xffffffff; /* 4G */
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resource->flags = IORESOURCE_MEM;
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}
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}
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static void set_agp_aperture(struct device *dev)
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{
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struct resource *resource;
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resource = probe_resource(dev, 0x94);
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if (resource) {
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struct device *pdev;
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struct device_id id;
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u32 gart_base, gart_acr;
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/* Remember this resource has been stored */
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resource->flags |= IORESOURCE_STORED;
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/* Find the size of the GART aperture */
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gart_acr = (0 << 6) | (0 << 5) | (0 << 4) |
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((resource->gran - 25) << 1) | (0 << 0);
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/* Get the base address */
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gart_base = ((resource->base) >> 25) & 0x00007fff;
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/* Update the other northbriges */
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pdev = NULL;
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id.type = DEVICE_ID_PCI;
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id.pci.vendor = PCI_VENDOR_ID_AMD;
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id.pci.device = 0x1103;
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while ((pdev = dev_find_device(&id, pdev))) {
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/* Store the GART size but don't enable it */
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pci_write_config32(pdev, 0x90, gart_acr);
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/* Store the GART base address */
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pci_write_config32(pdev, 0x94, gart_base);
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/* Don't set the GART Table base address */
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pci_write_config32(pdev, 0x98, 0);
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/* Report the resource has been stored... */
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report_resource_stored(pdev, resource, " <gart>");
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}
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}
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}
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static void mcf3_set_resources(struct device *dev)
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{
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printk(BIOS_DEBUG, "%s...\n", __func__);
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/* Set the GART aperture */
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set_agp_aperture(dev);
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/* Set the generic PCI resources */
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pci_set_resources(dev);
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}
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static void misc_control_init(struct device *dev)
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{
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u32 cmd, cmd_ref;
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int needs_reset;
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struct device *f0_dev;
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printk(BIOS_DEBUG, "NB: Function 3 Misc Control..\n");
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needs_reset = 0;
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/* Disable Machine checks from Invalid Locations.
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* This is needed for PC backwards compatibility.
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*/
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cmd = pci_read_config32(dev, 0x44);
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cmd |= (1 << 6) | (1 << 25);
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pci_write_config32(dev, 0x44, cmd);
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/* Optimize the Link read pointers */
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f0_dev = dev_find_slot(0, dev->path.pci.devfn - 3);
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if (f0_dev) {
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int link;
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cmd_ref = cmd = pci_read_config32(dev, 0xdc);
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for (link = 0; link < 3; link++) {
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u32 link_type;
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unsigned reg;
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/* This works on an Athlon64 because unimplemented
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* links return 0.
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*/
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reg = 0x98 + (link * 0x20);
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link_type = pci_read_config32(f0_dev, reg);
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/* Only handle coherent links here please. */
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if ((link_type &
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(LinkConnected | InitComplete | NonCoherent))
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== (LinkConnected | InitComplete)) {
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cmd &= ~(0xff << (link * 8));
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/* FIXME this assumes the device on the other
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* side is an AMD device.
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*/
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cmd |= 0x25 << (link * 8);
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}
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}
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if (cmd != cmd_ref) {
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pci_write_config32(dev, 0xdc, cmd);
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needs_reset = 1;
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}
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} else {
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printk(BIOS_ERR, "Missing f0 device!\n");
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}
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if (needs_reset) {
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printk(BIOS_DEBUG, "Not resetting cpu, but it's needed.\n");
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//hard_reset();
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}
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printk(BIOS_DEBUG, "done.\n");
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}
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struct device_operations mcf3_ops = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_AMD,
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.device = 0x1103}}},
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.phase3_scan = 0,
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.phase4_read_resources = mcf3_read_resources,
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.phase4_set_resources = mcf3_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = misc_control_init,
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.ops_pci = 0,
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};
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