Henrik Rydgard
bfed830f91
Remove the ability to disable rounding mode support. It's time.
2015-10-08 14:54:42 +02:00
Henrik Rydgard
6dd86cd843
Get rid of the ForceFlushToZero hidden config option
2015-10-08 14:54:41 +02:00
Henrik Rydgard
490d8be4df
Some cleanup, enable CRT memory tracker in debug builds
2015-10-04 14:11:34 +02:00
Henrik Rydgard
68fc776fa7
Work around some crashes I got trying to load a GTA:LCS savestate from 2014.
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However, the savestate still loads to a black screen, although background audio is working.
2015-10-04 10:34:15 +02:00
Henrik Rydgard
aaa8350591
Windows: Fix some remaining ASLR issues
2015-07-15 22:25:24 +02:00
Unknown W. Brackets
8fdceba7ca
Add timing for all the basics.
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This way we can see overall stats for a frame.
2015-07-03 12:05:08 -07:00
Unknown W. Brackets
66adc4e695
jit: Normalize CONDITIONAL_DISABLE formatting.
2015-07-02 20:31:37 -07:00
Unknown W. Brackets
b818509734
x86jit: Fix clobbering address in lv.q/sv.q.
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We can't let it go into EAX. Hmm, maybe there's a cleaner way.
Should fix #7686 .
2015-04-14 23:17:11 -07:00
Henrik Rydgård
a1f5c537d4
Merge pull request #7672 from unknownbrackets/jit-minor
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More x86jit micro optimizations for the FPU
2015-04-13 09:57:02 +02:00
Henrik Rydgård
c1b91ff5c1
x86: Add a way to eliminate some mov instructions.
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Not currently used yet.
2015-04-12 13:50:23 -07:00
Henrik Rydgård
70fa830ba5
Split out the ReplaceJalTo test logic.
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This makes it so the IR, in the future, can work correctly for
replacements.
2015-04-12 13:35:10 -07:00
Henrik Rydgård
d014d420db
Unify JitOptions across the backends.
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This is required to make ExtractIR not a member of the various backends.
2015-04-12 11:41:26 -07:00
Unknown W. Brackets
56f071d26a
x86jit: Support SIMD load/store with fastmem off.
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Which is a lot faster, since it usually takes the fast path.
2015-04-11 01:22:50 -07:00
Henrik Rydgård
81dec36da8
Use an accessor to read the compilerPC.
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In the IR it will be read from the block.
2015-04-11 01:14:37 -07:00
Henrik Rydgård
a897723e6a
Separate out jit reading nearby instructions.
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This makes it easier to use an IR for these things, or remove them.
2015-04-11 00:53:24 -07:00
Unknown W. Brackets
7ea9bcbc13
x86jit: Avoid mapping rs in vfpu load/store.
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This allows immediate address load/store, when possible, which can be
faster (especially with slow mem enabled.)
2015-04-10 20:30:14 -07:00
Unknown W. Brackets
eaed080add
x86jit: Fix immediate kernel addresses.
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Using a signed add + a value with the top bit set = bad. Will have to
live with losing the kernel bit here, should be fine.
2015-04-10 20:25:29 -07:00
Unknown W. Brackets
e58eb5e186
x86jit: Small optimization for fd->fd fp convert.
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We just generate a little less code. This is also slightly faster
generally.
2015-04-10 20:07:43 -07:00
Unknown W. Brackets
7e38df077f
x86jit: Prefer MOVAPS over MOVSS for reg->reg.
2015-04-10 20:07:43 -07:00
Unknown W. Brackets
9069c84928
x86jit: Use ANDPS for abs.s.
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Should be faster considering they're likely to use other floating point
math on it. As long as that's the case, this is faster than PAND.
2015-04-10 13:20:52 -07:00
Unknown W. Brackets
7ce5841f30
jit: Avoid mfhi/mflo to $0.
2015-04-07 18:25:28 -07:00
Unknown W. Brackets
788b9d78f8
jit: Avoid a super unlikely write to zero.
2015-04-07 18:20:37 -07:00
Unknown W. Brackets
bdd1db1fa2
x86jit: Handle vmin/vmax and vsge correctly.
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Unfortunately, this boots vmin/vmax from simd, currently.
2015-03-29 12:24:49 -07:00
Unknown W. Brackets
9d52ee4e21
Fix cases where breakpoints were skipped.
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After reset or savestate load.
2015-03-17 23:06:25 -07:00
Unknown W. Brackets
98d7afae89
Switch to #pragma once in a few places.
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Doesn't really affect git history much to change these.
2015-03-02 22:34:51 -08:00
Unknown W. Brackets
179e996b0b
jit: Discard unused regs before a syscall.
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This is a pretty minor optimization, though.
2015-03-01 11:08:59 -08:00
Chin
37f50a3792
Change to pass some arguments by reference
2015-03-01 16:49:00 +01:00
Henrik Rydgard
07933cad42
Revert "Minor optimizations, add a failsafe"
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This reverts commit 48e4d1edae
2015-01-22 19:52:58 +01:00
Henrik Rydgard
48e4d1edae
Minor optimizations, add a failsafe
2015-01-20 20:08:12 +01:00
Unknown W. Brackets
cdddd4b59c
Fix an undefined bit shift.
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Shouldn't have mattered anyway, but maybe this can crash some ARM chip or
something...
2015-01-19 08:40:10 -08:00
Unknown W. Brackets
9cb1151b67
x86jit: Disable replacements w/ breakpoints inside.
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This does alter graphics (memcpys won't fire anymore), but it also means
breakpoints work which is nice.
2015-01-18 21:26:37 -08:00
Unknown W. Brackets
0dc3e4e2db
x86jit: Handle unable to spill better.
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Might as well check the result to be safe.
2015-01-17 18:42:58 -08:00
Unknown W. Brackets
a27be3887e
x86jit: Handle overlap better in simd vtfm.
2015-01-07 18:10:53 -08:00
Henrik Rydgård
bb1d571493
Merge pull request #7261 from hilesaz/master
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Fix simd vmmul transpose optimizations.
2015-01-06 11:59:14 +01:00
Unknown W. Brackets
23893ffba8
x86jit: Fix crash in prefixes and simd enabled.
2015-01-04 15:50:12 -08:00
Henrik Rydgard
90376267b1
More reg number asserts
2015-01-04 23:15:33 +01:00
Henrik Rydgard
fe63a15e22
x86jit fpu regcache: Add extra invariant check for too-large mips register numbers
2015-01-04 22:54:01 +01:00
Bovine
54c7a12306
Fix simd vmmul transpose optimizations.
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Yep, gotta discard the S matrix when we're done with it.
2015-01-03 16:58:03 -07:00
Bovine
0fdebdc1ca
Fix discardVS.
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It's not valid for non-away values to have a lane.
2015-01-03 16:54:31 -07:00
Henrik Rydgard
3cc633f091
x86jit: Minor logging improvements in FPU recache
2015-01-03 22:55:39 +01:00
Bovine
185d4db081
Fix simd vmmul transpose optimizations.
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Need to ensure S has been written back before transposing it or we'll end
up writing back S'.
2015-01-03 14:48:54 -07:00
Henrik Rydgård
5fffe53671
Merge pull request #7258 from unknownbrackets/jit-minor
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x86jit: Fix vavg, improve vfad
2015-01-03 19:44:22 +01:00
Unknown W. Brackets
a1864b2c78
x86jit: Fix vavg scale.
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Was completely wrong, darn it.
2015-01-03 10:39:58 -08:00
Unknown W. Brackets
8a089ee583
x86jit: Handle -0.0 in vavg/vfad.
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Should result in a positive result.
2015-01-03 10:39:26 -08:00
Henrik Rydgard
13c4a22967
Disable transpose optimization, seems to break games
2015-01-02 01:13:34 +01:00
Henrik Rydgard
6a7e5d1cc2
x86 Jit SIMD: Generate somewhat shorter code for handling transposed matrices in vmmul.
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TODO: Build into regalloc instead, with a MapMatrix function?
2015-01-01 12:44:03 +01:00
Unknown W. Brackets
5f6f8ac0a2
x86jit: Fix another sequential detect problem.
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Arg. Maybe should use voffset after all, but it won't fit in a u8
anyway...
2014-12-31 22:43:31 -08:00
Unknown W. Brackets
c5f7b6fa72
x86jit: Disable simd again for now.
2014-12-31 19:43:40 -08:00
Henrik Rydgård
6bf2c02908
x86 jit: Allow storing all imms directly without bouncing to a register, not just zero.
2014-12-23 22:25:53 +01:00
Bovine
a9b7656f93
Fix to VFPU register allocation. Fixes #7174
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GetFreeXRegs(_,_,true) invalidates registers it can see on spill,
but it can't see all the registers in the array due to how we call it
so we have to invalidate the rest ourselves. Not doing so can get it
to use the same register twice.
2014-12-23 03:39:50 -07:00
