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x86jit fpu regcache: Add extra invariant check for too-large mips register numbers
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1 changed files with 5 additions and 0 deletions
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@ -615,6 +615,8 @@ static int MMShuffleSwapTo0(int lane) {
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void FPURegCache::StoreFromRegister(int i) {
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_assert_msg_(JIT, !regs[i].location.IsImm(), "WTF - FPURegCache::StoreFromRegister - it's an imm");
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_assert_msg_(JIT, i >= 0 && i < NUM_MIPS_FPRS, "WTF - FPURegCache::StoreFromRegister - invalid mipsreg %i PC=%08x", i, js_->compilerPC);
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if (regs[i].away) {
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X64Reg xr = regs[i].location.GetSimpleReg();
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_assert_msg_(JIT, xr >= 0 && xr < NUM_X_FPREGS, "WTF - FPURegCache::StoreFromRegister - invalid reg: x %i (mr: %i). PC=%08x", (int)xr, i, js_->compilerPC);
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@ -944,6 +946,9 @@ int FPURegCache::SanityCheck() const {
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hasMoreRegs = false;
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continue;
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}
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if (xr.mipsRegs[j] >= NUM_MIPS_FPRS) {
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return 13;
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}
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// We can't have a hole in the middle / front.
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if (!hasMoreRegs)
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return 9;
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