Emulation/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2025-04-02 11:01:50 -04:00
Code Issues Projects Releases Packages Wiki Activity
35718 commits 81 branches 122 tags 700 MiB
Commit graph

775 commits

Author SHA1 Message Date
Henrik Rydgard
32c81c3265 x86 jit vcrsp.t: Oops, don't "SimpleReg" before doing the SIMD solution.. 2014-11-28 01:06:32 +01:00
Henrik Rydgard
344f71b092 x86 jit: Commit commented-out haddps-based vdot.q as reminder not to use haddps... 2014-11-28 00:19:11 +01:00
Henrik Rydgard
8f4d322dc6 Another oops... 2014-11-27 23:33:03 +01:00
Henrik Rydgard
bcdfb496a0 Oops, bad merge 2014-11-27 23:12:57 +01:00
Henrik Rydgard
c5bf3adec0 x86 jit: use the correct fp move instruction, minor optimization in vdot 2014-11-27 23:08:15 +01:00
Unknown W. Brackets
0839ce59e1 x86jit: Apply dirty when reusing 1-reg VS. 2014-11-27 01:05:11 -08:00
Unknown W. Brackets
bbeb5758b7 x86jit: Simplify VS() / VSX() usage. 2014-11-27 00:07:17 -08:00
Unknown W. Brackets
039510a3e3 x86jit: Respect dirty even for non-simd. 2014-11-26 23:29:20 -08:00
Unknown W. Brackets
f63c165f64 x86jit: Fix several cases of missing dirty checks. 2014-11-26 23:28:14 -08:00
Henrik Rydgard
acb711007f x86 jit: SIMD-ify cross product 2014-11-27 00:18:19 +01:00
Henrik Rydgard
5033babb10 x86 Jit: SIMD-ify vdot 2014-11-26 23:47:18 +01:00
Henrik Rydgard
bbd0afd148 x86 jit: Disable SIMD by default, needs just a little more debugging.. 2014-11-26 22:30:41 +01:00
Henrik Rydgard
4b25afb7b4 x86 Jit: SIMD some more instructions 2014-11-26 22:30:06 +01:00
Henrik Rydgard
becdb14a3f x86 jit: Fix a couple issues in simd storefromregister 2014-11-26 22:25:18 +01:00
Henrik Rydgård
80797dc723 Merge pull request #7108 from unknownbrackets/jit-simd 
Fix the simd issue at least for Wipeout
 2014-11-26 21:42:02 +01:00
Unknown W. Brackets
abd425d9f1 x86jit: Re-enable the simd optimization. 2014-11-26 09:21:15 -08:00
Unknown W. Brackets
e5dabaabe2 x86jit: Optimize simd->non for 1-lane a little. 2014-11-26 09:20:50 -08:00
Unknown W. Brackets
5d0c32d1e6 x86jit: Assume non-simd regs are dirty. 2014-11-26 09:19:50 -08:00
Henrik Rydgard
804de50711 x86 jit: SIMD-ify VFPU register file writebacks where possible 2014-11-26 01:33:05 +01:00
Henrik Rydgard
b3c8a82c49 x86 jit: SIMD-ify some more 2014-11-25 23:56:46 +01:00
Henrik Rydgard
b5ee47a80c x86 jit: SIMD-ify lv.q and sv.q 2014-11-25 23:28:29 +01:00
Henrik Rydgård
4db6b7f3e2 SIMD-ify a couple instructions a bit 2014-11-25 22:47:26 +01:00
Unknown W. Brackets
a4b9122943 x86jit: Use NS instead of NBE for checked entries. 
This may cause us to more correctly bail on linked blocks in some cases.
 2014-11-23 11:05:49 -08:00
Unknown W. Brackets
fe525a52f9 Update native (shutdown crash) + comment. 2014-11-23 11:04:07 -08:00
Unknown W. Brackets
473f388088 Disable the simd stuff for now. 
Won't have time to look at this for a bit...
 2014-11-20 14:07:56 -08:00
Henrik Rydgård
6a49337a0c Merge pull request #7096 from unknownbrackets/jit-simd 
x86jit: Add basic support for mapping SIMD
 2014-11-18 18:25:39 +01:00
Unknown W. Brackets
ab7dd0df25 x86jit: Add an option to enable/disable vpfu simd. 2014-11-17 20:37:27 -08:00
Henrik Rydgard
53b5d331b4 Assorted minor optimizations 2014-11-17 21:21:44 +01:00
Unknown W. Brackets
921b39ebf5 x86jit: Optimize a 2-reg simd load. 2014-11-16 15:05:17 -08:00
Unknown W. Brackets
e68eb0a292 x86jit: Load sequential regs in one shot. 2014-11-16 15:05:17 -08:00
Unknown W. Brackets
ed501302a2 x86jit: Add a check to see if we can map simd. 2014-11-16 15:05:16 -08:00
Unknown W. Brackets
27148d3712 x86jit: Add some helpers to check state. 2014-11-16 13:33:16 -08:00
Unknown W. Brackets
de566be2ce x86jit: Split out the logic for loading simd regs. 2014-11-16 13:33:15 -08:00
Unknown W. Brackets
5347431c20 x86jit: Initial simd for VecDo3(). Broken. 
I'm not sure why/where it's broken...
 2014-11-16 13:33:15 -08:00
Unknown W. Brackets
aad505e7b3 x86jit: Add a TryMapDirtyInInVS() for 3-op. 2014-11-16 13:33:14 -08:00
Unknown W. Brackets
88a753eff3 x86jit: Add an invariant contract to the fpu cache. 
This should help catch things better in debug mode.
 2014-11-16 13:33:14 -08:00
Unknown W. Brackets
39afeb490f x86jit: Add some typesafety. 2014-11-16 13:33:13 -08:00
Unknown W. Brackets
4335bf3346 x86jit: Add basic mapping of SIMD regs. 
Not tested yet, just sketched out.  All very suboptimal.
 2014-11-16 13:33:13 -08:00
Unknown W. Brackets
9429359b47 x86jit: Add fallbacks when moving from VS -> V. 2014-11-16 13:33:12 -08:00
Unknown W. Brackets
2862367927 x86jit: Add force-non-simd to all current ops. 
Unless they already use MapRegs, because that will automatically handle
it.
 2014-11-16 13:33:12 -08:00
Unknown W. Brackets
4cf0913692 x86jit: Sketch some initial SIMD apis. 2014-11-16 13:33:07 -08:00
Henrik Rydgard
bfcd3690b6 x86 jit: Fix+enable quaternion product, optimize "sw zero, *" 2014-11-16 18:37:38 +01:00
Henrik Rydgard
28ca8d4818 x86 jit: Use LEA to emulate addu but only when it can save a few bytes 2014-11-16 17:39:47 +01:00
Henrik Rydgard
1c78e29c79 x86 jit: For clarity, use TEMPREG where it doesn't matter that it's EAX. 
Might have missed a few places.
 2014-11-16 17:38:26 +01:00
Henrik Rydgard
8b90f881b8 x86 jit: A tiny optimization and a tiny bugfix 2014-11-16 16:46:35 +01:00
Unknown W. Brackets
096b41cceb x86jit: Interleave reg usage in vcmp. 2014-11-10 23:22:04 -08:00
Unknown W. Brackets
0e1aa35e84 x86jit: Just do the ES/NS compare once. 2014-11-10 23:04:38 -08:00
Unknown W. Brackets
2758e8fa3c x86jit: Optimize vcmp for single and simd. 2014-11-10 23:04:37 -08:00
Unknown W. Brackets
86e3739a3e x86jit: Optimize some cases of ins/ext. 
They happen but are minor.
 2014-11-09 09:22:29 -08:00
Unknown W. Brackets
e05263af32 x86jit: Allow EBX sign extension for 32-bit. 2014-11-09 09:07:52 -08:00