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258 commits

Author SHA1 Message Date
Henrik Rydgård
c5e0b799d9 Remove category from _assert_msg_ functions. We don't filter these by category anyway. 
Fixes the inconsistency where we _assert_ didn't take a category but
_assert_msg_ did.
 2020-07-19 20:33:25 +02:00
Henrik Rydgard
c988d42b04 ARM/ARM64 instruction analysis, hook up to handler 2020-07-14 09:25:45 +02:00
Unknown W. Brackets
3c34c7c456 irjit: Add jump crash checks. 
Doesn't seem to have any significant impact on performance.
 2020-07-12 22:17:36 -07:00
Henrik Rydgård
8461ea19b1 Centralize handling of memory exceptions a bit 2020-07-12 15:25:20 +02:00
Unknown W. Brackets
5afc020fbd x86jit: Force INF * 0 to +NAN. 
See #12519 - this is needed for some graphics to render properly.  Seems
to already happen on ARM, so no change to armjit.
 2020-04-06 06:33:39 -07:00
Henrik Rydgård
f65a71d6d8 Compat: Option to use accurate dotprod for VMMUL. 
Eliminates Tekken 6 leg shaking.
 2019-08-05 11:44:52 -07:00
Henrik Rydgård
30831f3ea1 Implement and test clz32, use it in the MIPS interpreter cores. 
This will be useful for our vfpu-dot implementations later.
 2019-06-14 18:39:15 +02:00
Henrik Rydgård
7853c90abb JIT: Split VFPU_MTX disable options. To help with #9843 2019-06-03 23:28:15 +02:00
Unknown W. Brackets
c773359095 arm64jit: Tweak matrix vfpu overlap detect, etc. 
Tried making changes to them to guess at issues for #9843, but didn't find
any.  Still, I think these changes are worthwhile, if small.
 2019-06-02 22:10:20 -07:00
Henrik Rydgård
2f26297062 Clean up some more ifdefs 2019-05-10 23:25:57 +02:00
driver1998
5072584781 Fix neon headers for MSVC ARM64 
MSVC uses arm64_neon.h for ARM64, arm_neon.h is ARM32 only.
 2019-05-04 22:45:15 +08:00
Unknown W. Brackets
ec7cffa847 interp: Handle vtfm/vhtfm prefixes properly. 2019-04-02 18:46:39 -07:00
Unknown W. Brackets
5414c12a15 interp: Cleanup prefix/size in vcrsp/vqmul. 2019-04-02 07:12:34 -07:00
Henrik Rydgård
b346142df8
Merge pull request #11954 from unknownbrackets/vfpu-chunk5 
Fix prefix and size handling for vsbx, vsocp, and integer conv ops
 2019-04-01 17:12:03 +02:00
Unknown W. Brackets
b24f84d1a2 interp: Handle prefixes on matrix init ops. 2019-03-31 17:11:24 -07:00
Unknown W. Brackets
59905de719 interp: Correct vsgn out of swizzle bounds. 2019-03-31 17:10:51 -07:00
Unknown W. Brackets
b881a689c4 interp: Ignore high bit in vmfvc/vmtvc. 
Both 0 and 128 read/write the S prefix, for example.
 2019-03-31 17:09:55 -07:00
Unknown W. Brackets
175ceef583 interp: Cleanup vsocp size handling. 2019-03-31 13:52:07 -07:00
Unknown W. Brackets
4a2f8a74dc interp: Correct size handling for vi2x ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
b75690787e interp: Correct swizzle on vx2i ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
68cdcba6c5 interp: Don't write lane 2 on single colorconv. 
Not that it's valid to use the op with that size anyway.
 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
5749ae09d0 interp: Correct vmfvc register behavior. 
The target and source registers were completely wrong.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
b2e024025f interp: Handle wrong sizes of vf2h/vh2f. 
Probably not ever used, but they have consistent behavior.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
af3ed69144 interp: Mask moves to vfpu ctrl. 
These bits of the registers can't be written.
 2019-03-31 10:37:07 -07:00
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d40ac043d4 interp: Handle prefixes for Vmmov/Vmmul/Vmscl. 
I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
ec1dae57eb interp: Fix vbfy prefix handling. 2019-03-31 10:09:18 -07:00
Unknown W. Brackets
d5273f589a interp: Mask value in vpfxd. 
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
 2019-03-31 08:23:36 -07:00
Unknown W. Brackets
7dc775e54f IR: Use interp for unhandled prefix cases. 
The interpreter is not changed yet, so in theory this shouldn't change
behavior.
 2019-03-31 08:17:11 -07:00
Unknown W. Brackets
4c3aa841d3 IR: Correct vmmul optimizations. 
It's a bit confusing since it's not D = S*T, but rather D = S'*T.
 2019-03-23 15:31:10 -07:00
Unknown W. Brackets
6178a1fb33 Jit: Correct vocp prefix handling. 
See #5549.  Matches tests for various prefix settings.
 2019-02-23 09:15:26 -08:00
Unknown W. Brackets
d7f40afd9d interp: Correct vocp prefix handling. 
Also, guess that vsocp also applies prefixes.  See #5549.
 2019-02-21 19:02:16 -08:00
Unknown W. Brackets
419c1fbd73 Jit: Respect flags for jit types and features. 
Left some free space for more.
 2019-02-03 14:57:08 -08:00
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46649a218e Core: Add flags to disable jit features. 
Not actually disabling yet, just setup.
 2019-02-03 13:58:24 -08:00
Henrik Rydgård
b4721fbc44 Temporary workaround for another IR interpreter crash. See #10897 2018-04-11 11:55:12 +02:00
Henrik Rydgård
3322adbc22 IR Interpreter: Add some missing instruction metadata. May help part of #10897 2018-04-11 11:16:41 +02:00
Unknown W. Brackets
ab809bd19e jit: Apply hasSetRounding at compile time. 
Otherwise, the block will be executed with the wrong rounding mode the
first time rounding is set.  This could be important if it was set for a
single operation.

This is only a problem the first time it's set.
 2018-04-01 10:36:16 -07:00
Unknown W. Brackets
09e307b097 arm64jit: Update rounding mode on thread switch. 
Since fcr31 is per-thread, we must update jit state when it changes.
This also fixes the rounding mode on load state and jit/interp switch.
 2018-04-01 10:12:32 -07:00
Henrik Rydgård
34f79904fd IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily. 2018-01-10 09:19:27 +01:00
Henrik Rydgård
fb0e81484b Minor cleanup 2018-01-10 09:19:27 +01:00
Henrik Rydgård
4a32ec3102
Merge pull request #10516 from unknownbrackets/irjit-lwr 
irjit: Optimize out more temps and lwl/lwr operations
 2018-01-10 09:11:10 +01:00
Unknown W. Brackets
b6bb0159e3 irjit: Remove Comp_ITypeMemLR. 2018-01-09 18:06:25 -08:00
Unknown W. Brackets
f01e06aefd irjit: Improve multiple lwr in a row. 2018-01-07 21:06:02 -08:00
Unknown W. Brackets
fbeedd333b irjit: Swap moves when it may allow clobbering. 
Example:
addiu a0, a1, a2
mov s0, a0
addiu a0, a2, a3

By swapping the mov, we can eliminate it.

Only going one back because it's common and didn't want to track reads.
 2018-01-07 21:06:02 -08:00
Unknown W. Brackets
d27e428659 irjit: Convert lwr and friends to easier code. 
This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
 2018-01-07 21:06:00 -08:00
Unknown W. Brackets
b11f00cead irjit: Combine lwl/lwr and swl/swr, like before. 
Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
 2018-01-07 21:05:58 -08:00
Unknown W. Brackets
c6d690e9b8 irjit: Handle Left/Right ops in passes. 2018-01-07 21:05:57 -08:00
Unknown W. Brackets
6dda053365 irjit: Add dedicated ops for lwl/swl and friends. 
Temporarily removes optimizations.
 2018-01-07 21:05:57 -08:00
Unknown W. Brackets
cd3f4881a5 irjit: Optimize out temp lhs copies. 
Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2

Which was copying s2 before.  This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
 2018-01-07 12:11:16 -08:00
Unknown W. Brackets
97674b80bd irjit: Skip preloading blocks with jump to 0. 
These will be changed before executing anyway.
 2018-01-06 17:23:53 -08:00
Unknown W. Brackets
cc8e9a93c3 irjit: For debug, return the best block at addr. 
Invalidation may result in multiple matching blocks, prefer any that is
currently valid.
 2018-01-06 17:08:54 -08:00