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Jit: Respect flags for jit types and features.

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Left some free space for more.
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Unknown W. Brackets 2019-02-03 14:01:51 -08:00
parent 46649a218e
commit 419c1fbd73
17 changed files with 248 additions and 246 deletions
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18
Core/MIPS/ARM/ArmCompALU.cpp
View file

@ -43,7 +43,7 @@ using namespace MIPSAnalyst;
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp
@ -72,7 +72,7 @@ namespace MIPSComp
void ArmJit::Comp_IType(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_IMM);
s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension
u32 uimm = op & 0xFFFF;
u32 suimm = (u32)(s32)simm;
@ -150,7 +150,7 @@ namespace MIPSComp
void ArmJit::Comp_RType2(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
@ -234,7 +234,7 @@ namespace MIPSComp
void ArmJit::Comp_RType3(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
@ -502,7 +502,7 @@ namespace MIPSComp
void ArmJit::Comp_ShiftType(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU);
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
int fd = _FD;
@ -529,7 +529,7 @@ namespace MIPSComp
void ArmJit::Comp_Special3(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rs = _RS;
MIPSGPReg rt = _RT;
@ -591,7 +591,7 @@ namespace MIPSComp
void ArmJit::Comp_Allegrex(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rt = _RT;
MIPSGPReg rd = _RD;
// Don't change $zr.
@ -645,7 +645,7 @@ namespace MIPSComp
void ArmJit::Comp_Allegrex2(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rt = _RT;
MIPSGPReg rd = _RD;
// Don't change $zr.
@ -677,7 +677,7 @@ namespace MIPSComp
void ArmJit::Comp_MulDivType(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(MULDIV);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;

12
Core/MIPS/ARM/ArmCompFPU.cpp
View file

@ -44,7 +44,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp
@ -54,7 +54,7 @@ namespace MIPSComp
void ArmJit::Comp_FPU3op(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU);
int ft = _FT;
int fs = _FS;
@ -92,7 +92,7 @@ extern int logBlocks;
void ArmJit::Comp_FPULS(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_FPU);
CheckMemoryBreakpoint();
s32 offset = (s16)(op & 0xFFFF);
@ -193,7 +193,7 @@ void ArmJit::Comp_FPULS(MIPSOpcode op)
}
void ArmJit::Comp_FPUComp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU_COMP);
int opc = op & 0xF;
if (opc >= 8) opc -= 8; // alias
@ -258,7 +258,7 @@ void ArmJit::Comp_FPUComp(MIPSOpcode op) {
}
void ArmJit::Comp_FPU2op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU);
int fs = _FS;
int fd = _FD;
@ -350,7 +350,7 @@ void ArmJit::Comp_FPU2op(MIPSOpcode op) {
void ArmJit::Comp_mxc1(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU_XFER);
int fs = _FS;
MIPSGPReg rt = _RT;

8
Core/MIPS/ARM/ArmCompLoadStore.cpp
View file

@ -42,7 +42,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp
@ -111,14 +111,14 @@ namespace MIPSComp
}
void ArmJit::Comp_ITypeMemLR(MIPSOpcode op, bool load) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
CheckMemoryBreakpoint();
int offset = (signed short)(op & 0xFFFF);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
int o = op >> 26;
if (!js.inDelaySlot) {
if (!js.inDelaySlot && !jo.Disabled(JitDisable::LSU_UNALIGNED)) {
// Optimisation: Combine to single unaligned load/store
bool isLeft = (o == 34 || o == 42);
CheckMemoryBreakpoint(1);
@ -260,7 +260,7 @@ namespace MIPSComp
void ArmJit::Comp_ITypeMem(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
CheckMemoryBreakpoint();
int offset = (signed short)(op&0xFFFF);
bool load = false;

66
Core/MIPS/ARM/ArmCompVFPU.cpp
View file

@ -40,7 +40,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
#define NEON_IF_AVAILABLE(func) { if (jo.useNEONVFPU) { func(op); return; } }
@ -87,7 +87,7 @@ namespace MIPSComp
void ArmJit::Comp_VPFX(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int data = op & 0xFFFFF;
int regnum = (op >> 24) & 3;
switch (regnum) {
@ -225,7 +225,7 @@ namespace MIPSComp
void ArmJit::Comp_SV(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_SV);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
CheckMemoryBreakpoint();
s32 offset = (signed short)(op & 0xFFFC);
@ -332,7 +332,7 @@ namespace MIPSComp
void ArmJit::Comp_SVQ(MIPSOpcode op)
{
NEON_IF_AVAILABLE(CompNEON_SVQ);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
CheckMemoryBreakpoint();
int imm = (signed short)(op&0xFFFC);
@ -478,7 +478,7 @@ namespace MIPSComp
void ArmJit::Comp_VVectorInit(MIPSOpcode op)
{
NEON_IF_AVAILABLE(CompNEON_VVectorInit);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
// WARNING: No prefix support!
if (js.HasUnknownPrefix()) {
DISABLE;
@ -515,7 +515,7 @@ namespace MIPSComp
void ArmJit::Comp_VIdt(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_VIdt);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -553,7 +553,7 @@ namespace MIPSComp
void ArmJit::Comp_VMatrixInit(MIPSOpcode op)
{
NEON_IF_AVAILABLE(CompNEON_VMatrixInit);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
// Don't think matrix init ops care about prefixes.
// DISABLE;
@ -601,7 +601,7 @@ namespace MIPSComp
void ArmJit::Comp_VHdp(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_VHdp);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -644,7 +644,7 @@ namespace MIPSComp
void ArmJit::Comp_Vhoriz(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vhoriz);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -687,7 +687,7 @@ namespace MIPSComp
void ArmJit::Comp_VDot(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_VDot);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -724,7 +724,7 @@ namespace MIPSComp
void ArmJit::Comp_VecDo3(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_VecDo3);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -884,7 +884,7 @@ namespace MIPSComp
void ArmJit::Comp_VV2Op(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_VV2Op);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1077,7 +1077,7 @@ namespace MIPSComp
void ArmJit::Comp_Vi2f(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vi2f);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1124,7 +1124,7 @@ namespace MIPSComp
void ArmJit::Comp_Vh2f(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vh2f);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1186,7 +1186,7 @@ namespace MIPSComp
void ArmJit::Comp_Vf2i(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vf2i);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
@ -1256,7 +1256,7 @@ namespace MIPSComp
void ArmJit::Comp_Mftv(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Mftv);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int imm = op & 0xFF;
MIPSGPReg rt = _RT;
@ -1331,7 +1331,7 @@ namespace MIPSComp
void ArmJit::Comp_Vmfvc(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vmtvc);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int vs = _VS;
int imm = op & 0xFF;
@ -1350,7 +1350,7 @@ namespace MIPSComp
void ArmJit::Comp_Vmtvc(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vmtvc);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int vs = _VS;
int imm = op & 0xFF;
@ -1377,7 +1377,7 @@ namespace MIPSComp
void ArmJit::Comp_Vmmov(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vmmov);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// This probably ignores prefixes for all sane intents and purposes.
if (_VS == _VD) {
@ -1415,7 +1415,7 @@ namespace MIPSComp
void ArmJit::Comp_VScl(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_VScl);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1464,7 +1464,7 @@ namespace MIPSComp
}
void ArmJit::Comp_Vmmul(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1513,7 +1513,7 @@ namespace MIPSComp
void ArmJit::Comp_Vtfm(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vtfm);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1584,7 +1584,7 @@ namespace MIPSComp
void ArmJit::Comp_Vi2x(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vi2x);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1662,7 +1662,7 @@ namespace MIPSComp
void ArmJit::Comp_Vx2i(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vx2i);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1751,7 +1751,7 @@ namespace MIPSComp
void ArmJit::Comp_VCrossQuat(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_VCrossQuat);
// This op does not support prefixes anyway.
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1831,7 +1831,7 @@ namespace MIPSComp
void ArmJit::Comp_Vcmp(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vcmp);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix())
DISABLE;
@ -2019,7 +2019,7 @@ namespace MIPSComp
void ArmJit::Comp_Vcmov(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vcmov);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -2070,7 +2070,7 @@ namespace MIPSComp
void ArmJit::Comp_Viim(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Viim);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -2088,7 +2088,7 @@ namespace MIPSComp
void ArmJit::Comp_Vfim(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vfim);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -2108,7 +2108,7 @@ namespace MIPSComp
void ArmJit::Comp_Vcst(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vcst);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -2178,7 +2178,7 @@ namespace MIPSComp
void ArmJit::Comp_VRot(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_VRot);
// VRot probably doesn't accept prefixes anyway.
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -2244,7 +2244,7 @@ namespace MIPSComp
void ArmJit::Comp_Vsgn(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vsgn);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -2293,7 +2293,7 @@ namespace MIPSComp
void ArmJit::Comp_Vocp(MIPSOpcode op) {
NEON_IF_AVAILABLE(CompNEON_Vocp);
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}

55
Core/MIPS/ARM/ArmCompVFPUNEON.cpp
View file

@ -53,7 +53,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
#define DISABLE_UNKNOWN_PREFIX { WLOG("DISABLE: Unknown Prefix in %s", __FUNCTION__); fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
@ -82,7 +82,7 @@ static const float zero = 0.0f;
void ArmJit::CompNEON_VecDo3(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -158,7 +158,7 @@ void ArmJit::CompNEON_VecDo3(MIPSOpcode op) {
// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
void ArmJit::CompNEON_SV(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
CheckMemoryBreakpoint();
// Remember to use single lane stores here and not VLDR/VSTR - switching usage
@ -276,7 +276,7 @@ inline int MIPS_GET_VQVT(u32 op) {
}
void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
CheckMemoryBreakpoint();
int offset = (signed short)(op & 0xFFFC);
@ -425,7 +425,7 @@ void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
}
void ArmJit::CompNEON_VVectorInit(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
// WARNING: No prefix support!
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
@ -450,7 +450,7 @@ void ArmJit::CompNEON_VVectorInit(MIPSOpcode op) {
}
void ArmJit::CompNEON_VDot(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -484,7 +484,7 @@ void ArmJit::CompNEON_VDot(MIPSOpcode op) {
void ArmJit::CompNEON_VHdp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -496,7 +496,7 @@ void ArmJit::CompNEON_VHdp(MIPSOpcode op) {
}
void ArmJit::CompNEON_VScl(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -515,7 +515,7 @@ void ArmJit::CompNEON_VScl(MIPSOpcode op) {
}
void ArmJit::CompNEON_VV2Op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -666,7 +666,7 @@ void ArmJit::CompNEON_VV2Op(MIPSOpcode op) {
}
void ArmJit::CompNEON_Mftv(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int imm = op & 0xFF;
MIPSGPReg rt = _RT;
switch ((op >> 21) & 0x1f) {
@ -746,7 +746,7 @@ void ArmJit::CompNEON_Vmfvc(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vmtvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int vs = _VS;
int imm = op & 0xFF;
@ -767,7 +767,7 @@ void ArmJit::CompNEON_Vmtvc(MIPSOpcode op) {
}
void ArmJit::CompNEON_VMatrixInit(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
MatrixSize msz = GetMtxSize(op);
int n = GetMatrixSide(msz);
@ -828,7 +828,7 @@ void ArmJit::CompNEON_VMatrixInit(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vmmov(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
if (_VS == _VD) {
// A lot of these no-op matrix moves in Wipeout... Just drop the instruction entirely.
return;
@ -856,7 +856,7 @@ void ArmJit::CompNEON_Vmmov(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vmmul(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
MatrixSize msz = GetMtxSize(op);
int n = GetMatrixSide(msz);
@ -895,7 +895,7 @@ void ArmJit::CompNEON_Vmmul(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vmscl(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
MatrixSize msz = GetMtxSize(op);
@ -920,7 +920,7 @@ void ArmJit::CompNEON_Vmscl(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vtfm(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -986,7 +986,7 @@ void ArmJit::CompNEON_Vf2i(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vi2f(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1012,6 +1012,7 @@ void ArmJit::CompNEON_Vi2f(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vh2f(MIPSOpcode op) {
CONDITIONAL_DISABLE(VFPU_VEC);
if (!cpu_info.bHalf) {
// No hardware support for half-to-float, fallback to interpreter
// TODO: Translate the fast SSE solution to standard integer/VFP stuff
@ -1045,7 +1046,7 @@ void ArmJit::CompNEON_Vh2f(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vcst(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -1063,7 +1064,7 @@ void ArmJit::CompNEON_Vcst(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vhoriz(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -1102,7 +1103,7 @@ void ArmJit::CompNEON_Vhoriz(MIPSOpcode op) {
}
void ArmJit::CompNEON_VRot(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
@ -1121,7 +1122,7 @@ void ArmJit::CompNEON_VRot(MIPSOpcode op) {
}
void ArmJit::CompNEON_VIdt(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -1167,7 +1168,7 @@ void ArmJit::CompNEON_VIdt(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vcmp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix())
DISABLE;
@ -1298,7 +1299,7 @@ void ArmJit::CompNEON_Vcmp(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vcmov(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1341,7 +1342,7 @@ void ArmJit::CompNEON_Vcmov(MIPSOpcode op) {
}
void ArmJit::CompNEON_Viim(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1358,7 +1359,7 @@ void ArmJit::CompNEON_Viim(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vfim(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1379,7 +1380,7 @@ void ArmJit::CompNEON_Vfim(MIPSOpcode op) {
// https://code.google.com/p/bullet/source/browse/branches/PhysicsEffects/include/vecmath/neon/vectormath_neon_assembly_implementations.S?r=2488
void ArmJit::CompNEON_VCrossQuat(MIPSOpcode op) {
// This op does not support prefixes anyway.
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE_UNKNOWN_PREFIX;
}
@ -1427,7 +1428,7 @@ void ArmJit::CompNEON_Vsgn(MIPSOpcode op) {
}
void ArmJit::CompNEON_Vocp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}

18
Core/MIPS/ARM64/Arm64CompALU.cpp
View file

@ -44,7 +44,7 @@ using namespace MIPSAnalyst;
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp {
@ -70,7 +70,7 @@ void Arm64Jit::CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, void (ARM64XEm
}
void Arm64Jit::Comp_IType(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_IMM);
s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension
u32 uimm = op & 0xFFFF;
u32 suimm = (u32)(s32)simm;
@ -146,7 +146,7 @@ void Arm64Jit::Comp_IType(MIPSOpcode op) {
}
void Arm64Jit::Comp_RType2(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
@ -234,7 +234,7 @@ void Arm64Jit::CompType3(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, void (ARM64XE
}
void Arm64Jit::Comp_RType3(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -406,7 +406,7 @@ void Arm64Jit::CompShiftVar(MIPSOpcode op, Arm64Gen::ShiftType shiftType) {
}
void Arm64Jit::Comp_ShiftType(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU);
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
int fd = _FD;
@ -431,7 +431,7 @@ void Arm64Jit::Comp_ShiftType(MIPSOpcode op) {
}
void Arm64Jit::Comp_Special3(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rs = _RS;
MIPSGPReg rt = _RT;
@ -479,7 +479,7 @@ void Arm64Jit::Comp_Special3(MIPSOpcode op) {
}
void Arm64Jit::Comp_Allegrex(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rt = _RT;
MIPSGPReg rd = _RD;
// Don't change $zr.
@ -529,7 +529,7 @@ void Arm64Jit::Comp_Allegrex(MIPSOpcode op) {
}
void Arm64Jit::Comp_Allegrex2(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rt = _RT;
MIPSGPReg rd = _RD;
// Don't change $zr.
@ -560,7 +560,7 @@ void Arm64Jit::Comp_Allegrex2(MIPSOpcode op) {
}
void Arm64Jit::Comp_MulDivType(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(MULDIV);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;

12
Core/MIPS/ARM64/Arm64CompFPU.cpp
View file

@ -52,7 +52,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp {
@ -60,7 +60,7 @@ namespace MIPSComp {
using namespace Arm64JitConstants;
void Arm64Jit::Comp_FPU3op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU);
int ft = _FT;
int fs = _FS;
@ -80,7 +80,7 @@ void Arm64Jit::Comp_FPU3op(MIPSOpcode op) {
void Arm64Jit::Comp_FPULS(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_FPU);
CheckMemoryBreakpoint();
// Surprisingly, these work fine alraedy.
@ -152,7 +152,7 @@ void Arm64Jit::Comp_FPULS(MIPSOpcode op)
}
void Arm64Jit::Comp_FPUComp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU_COMP);
int opc = op & 0xF;
if (opc >= 8) opc -= 8; // alias
@ -198,7 +198,7 @@ void Arm64Jit::Comp_FPUComp(MIPSOpcode op) {
}
void Arm64Jit::Comp_FPU2op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU);
int fs = _FS;
int fd = _FD;
@ -301,7 +301,7 @@ void Arm64Jit::Comp_FPU2op(MIPSOpcode op) {
void Arm64Jit::Comp_mxc1(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU_XFER);
int fs = _FS;
MIPSGPReg rt = _RT;

8
Core/MIPS/ARM64/Arm64CompLoadStore.cpp
View file

@ -42,7 +42,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp {
@ -110,14 +110,14 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_ITypeMemLR(MIPSOpcode op, bool load) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
CheckMemoryBreakpoint();
int offset = (signed short)(op & 0xFFFF);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
int o = op >> 26;
if (!js.inDelaySlot) {
if (!js.inDelaySlot && !jo.Disabled(JitDisable::LSU_UNALIGNED)) {
// Optimisation: Combine to single unaligned load/store
bool isLeft = (o == 34 || o == 42);
CheckMemoryBreakpoint(1);
@ -256,7 +256,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_ITypeMem(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
CheckMemoryBreakpoint();
int offset = (signed short)(op & 0xFFFF);

61
Core/MIPS/ARM64/Arm64CompVFPU.cpp
View file

@ -38,7 +38,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
#define _RS MIPS_GET_RS(op)
@ -80,7 +80,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VPFX(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int data = op & 0xFFFFF;
int regnum = (op >> 24) & 3;
switch (regnum) {
@ -201,7 +201,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_SV(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
CheckMemoryBreakpoint();
s32 offset = (signed short)(op & 0xFFFC);
@ -275,7 +275,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_SVQ(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
CheckMemoryBreakpoint();
int imm = (signed short)(op&0xFFFC);
@ -359,7 +359,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VVectorInit(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
// WARNING: No prefix support!
if (js.HasUnknownPrefix()) {
DISABLE;
@ -393,7 +393,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VIdt(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -428,7 +428,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VMatrixInit(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
// Don't think matrix init ops care about prefixes.
// DISABLE;
@ -475,7 +475,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VHdp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -517,7 +517,7 @@ namespace MIPSComp {
alignas(16) static const float vavg_table[4] = { 1.0f, 1.0f / 2.0f, 1.0f / 3.0f, 1.0f / 4.0f };
void Arm64Jit::Comp_Vhoriz(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -559,7 +559,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VDot(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -595,7 +595,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VecDo3(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -744,7 +744,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VV2Op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -884,7 +884,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vi2f(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -931,7 +931,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vh2f(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -978,6 +978,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Mftv(MIPSOpcode op) {
CONDITIONAL_DISABLE(VFPU_XFER);
int imm = op & 0xFF;
MIPSGPReg rt = _RT;
switch ((op >> 21) & 0x1f) {
@ -1063,7 +1064,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vmfvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int vs = _VS;
int imm = op & 0xFF;
@ -1081,7 +1082,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vmtvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int vs = _VS;
int imm = op & 0xFF;
@ -1107,7 +1108,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vmmov(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// This probably ignores prefixes for all sane intents and purposes.
if (_VS == _VD) {
@ -1144,7 +1145,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_VScl(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1193,7 +1194,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vmmul(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1239,7 +1240,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vtfm(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1307,7 +1308,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vi2x(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1376,7 +1377,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vx2i(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1471,7 +1472,7 @@ namespace MIPSComp {
void Arm64Jit::Comp_VCrossQuat(MIPSOpcode op) {
// This op does not support prefixes anyway.
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1550,7 +1551,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vcmp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix())
DISABLE;
@ -1727,7 +1728,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vcmov(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1778,7 +1779,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Viim(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1795,7 +1796,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vfim(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1814,7 +1815,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vcst(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1882,7 +1883,7 @@ namespace MIPSComp {
// calling the math library.
void Arm64Jit::Comp_VRot(MIPSOpcode op) {
// VRot probably doesn't accept prefixes anyway.
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1943,7 +1944,7 @@ namespace MIPSComp {
}
void Arm64Jit::Comp_Vocp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}

18
Core/MIPS/IR/IRCompALU.cpp
View file

@ -38,14 +38,14 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (opts.disableFlags & (uint32_t)JitDisable::flag) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
#define INVALIDOP { Comp_Generic(op); return; }
namespace MIPSComp {
void IRFrontend::Comp_IType(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_IMM);
s32 simm = (s32)_IMM16; // sign extension
u32 uimm = (u16)_IMM16;
@ -87,7 +87,7 @@ void IRFrontend::Comp_IType(MIPSOpcode op) {
}
void IRFrontend::Comp_RType2(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
@ -111,7 +111,7 @@ void IRFrontend::Comp_RType2(MIPSOpcode op) {
}
void IRFrontend::Comp_RType3(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -197,7 +197,7 @@ void IRFrontend::CompShiftVar(MIPSOpcode op, IROp shiftOp) {
}
void IRFrontend::Comp_ShiftType(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU);
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
int sa = _SA;
@ -222,7 +222,7 @@ void IRFrontend::Comp_ShiftType(MIPSOpcode op) {
}
void IRFrontend::Comp_Special3(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rs = _RS;
MIPSGPReg rt = _RT;
@ -265,7 +265,7 @@ void IRFrontend::Comp_Special3(MIPSOpcode op) {
void IRFrontend::Comp_Allegrex(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rt = _RT;
MIPSGPReg rd = _RD;
@ -293,7 +293,7 @@ void IRFrontend::Comp_Allegrex(MIPSOpcode op) {
}
void IRFrontend::Comp_Allegrex2(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rt = _RT;
MIPSGPReg rd = _RD;
@ -315,7 +315,7 @@ void IRFrontend::Comp_Allegrex2(MIPSOpcode op) {
}
void IRFrontend::Comp_MulDivType(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(MULDIV);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;

12
Core/MIPS/IR/IRCompFPU.cpp
View file

@ -49,14 +49,14 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (opts.disableFlags & (uint32_t)JitDisable::flag) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
#define INVALIDOP { Comp_Generic(op); return; }
namespace MIPSComp {
void IRFrontend::Comp_FPU3op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU);
int ft = _FT;
int fs = _FS;
@ -74,7 +74,7 @@ void IRFrontend::Comp_FPU3op(MIPSOpcode op) {
}
void IRFrontend::Comp_FPULS(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_FPU);
s32 offset = _IMM16;
int ft = _FT;
MIPSGPReg rs = _RS;
@ -97,7 +97,7 @@ void IRFrontend::Comp_FPULS(MIPSOpcode op) {
}
void IRFrontend::Comp_FPUComp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU_COMP);
int opc = op & 0xF;
if (opc >= 8) opc -= 8; // alias
@ -139,7 +139,7 @@ void IRFrontend::Comp_FPUComp(MIPSOpcode op) {
}
void IRFrontend::Comp_FPU2op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU);
int fs = _FS;
int fd = _FD;
@ -185,7 +185,7 @@ void IRFrontend::Comp_FPU2op(MIPSOpcode op) {
}
void IRFrontend::Comp_mxc1(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU_XFER);
int fs = _FS;
MIPSGPReg rt = _RT;

6
Core/MIPS/IR/IRCompLoadStore.cpp
View file

@ -39,13 +39,13 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (opts.disableFlags & (uint32_t)JitDisable::flag) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
#define INVALIDOP { Comp_Generic(op); return; }
namespace MIPSComp {
void IRFrontend::Comp_ITypeMem(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
int offset = _IMM16;
MIPSGPReg rt = _RT;
@ -106,7 +106,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Cache(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
// int imm = (s16)(op & 0xFFFF);
// int rs = _RS;

76
Core/MIPS/IR/IRCompVFPU.cpp
View file

@ -35,7 +35,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (opts.disableFlags & (uint32_t)JitDisable::flag) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
#define INVALIDOP { Comp_Generic(op); return; }
@ -109,7 +109,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VPFX(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int data = op & 0xFFFFF;
int regnum = (op >> 24) & 3;
switch (regnum) {
@ -274,7 +274,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_SV(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
s32 offset = (signed short)(op & 0xFFFC);
int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);
MIPSGPReg rs = _RS;
@ -296,7 +296,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_SVQ(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
int imm = (signed short)(op & 0xFFFC);
int vt = (((op >> 16) & 0x1f)) | ((op & 1) << 5);
MIPSGPReg rs = _RS;
@ -342,7 +342,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VVectorInit(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -368,7 +368,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VIdt(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -406,7 +406,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VMatrixInit(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
MatrixSize sz = GetMtxSize(op);
if (sz != M_4x4) {
DISABLE;
@ -447,7 +447,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VHdp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -487,7 +487,7 @@ namespace MIPSComp {
alignas(16) static const float vavg_table[4] = { 1.0f, 1.0f / 2.0f, 1.0f / 3.0f, 1.0f / 4.0f };
void IRFrontend::Comp_Vhoriz(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -524,7 +524,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VDot(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -562,7 +562,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VecDo3(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -721,7 +721,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VV2Op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -847,7 +847,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vi2f(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -894,7 +894,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vh2f(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
// Vector expand half to float
// d[N*2] = float(lowerhalf(s[N])), d[N*2+1] = float(upperhalf(s[N]))
@ -903,7 +903,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vf2i(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
// Vector float to integer
// d[N] = int(S[N] * mult)
@ -913,7 +913,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Mftv(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int imm = op & 0xFF;
MIPSGPReg rt = _RT;
@ -966,7 +966,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vmfvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
// Vector Move from vector control reg (no prefixes)
// S[0] = VFPU_CTRL[i]
@ -982,7 +982,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vmtvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
// Vector Move to vector control reg (no prefixes)
// VFPU_CTRL[i] = S[0]
@ -1004,7 +1004,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vmmov(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// Matrix move (no prefixes)
// D[N,M] = S[N,M]
@ -1061,7 +1061,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vmscl(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// Matrix scale, matrix by scalar (no prefixes)
// d[N,M] = s[N,M] * t[0]
@ -1099,7 +1099,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VScl(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1173,7 +1173,7 @@ namespace MIPSComp {
// This may or may not be a win when using the IR interpreter...
// Many more instructions to interpret.
void IRFrontend::Comp_Vmmul(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// Matrix multiply (no prefixes)
// D[0 .. N,0 .. M] = S[0 .. N, 0 .. M] * T[0 .. N,0 .. M]
@ -1256,7 +1256,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vtfm(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// Vertex transform, vector by matrix (no prefixes)
// d[N] = s[N*m .. N*m + n-1] dot t[0 .. n-1]
@ -1358,7 +1358,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VCrs(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1372,7 +1372,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VDet(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1385,7 +1385,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vi2x(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1470,7 +1470,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vx2i(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1570,7 +1570,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_VCrossQuat(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
// TODO: Does this instruction even look at prefixes at all?
if (js.HasUnknownPrefix())
DISABLE;
@ -1627,7 +1627,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vcmp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix())
DISABLE;
@ -1651,7 +1651,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vcmov(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1690,7 +1690,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Viim(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -1705,7 +1705,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vfim(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -1723,7 +1723,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vcst(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -1747,7 +1747,7 @@ namespace MIPSComp {
// Very heavily used by FF:CC. Should be replaced by a fast approximation instead of
// calling the math library.
void IRFrontend::Comp_VRot(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (!js.HasNoPrefix()) {
// Prefixes work strangely for this:
// * They never apply to cos (whether d or s prefixes.)
@ -1797,7 +1797,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vsgn(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1835,7 +1835,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vocp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -1872,7 +1872,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_ColorConv(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1883,7 +1883,7 @@ namespace MIPSComp {
}
void IRFrontend::Comp_Vbfy(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;

20
Core/MIPS/x86/CompALU.cpp
View file

@ -40,8 +40,8 @@ using namespace MIPSAnalyst;
// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
// #define CONDITIONAL_DISABLE(ignore) { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp
@ -74,7 +74,7 @@ namespace MIPSComp
void Jit::Comp_IType(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_IMM);
s32 simm = (s32)_IMM16; // sign extension
u32 uimm = op & 0xFFFF;
u32 suimm = (u32)(s32)simm;
@ -197,7 +197,7 @@ namespace MIPSComp
void Jit::Comp_RType2(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
@ -378,7 +378,7 @@ namespace MIPSComp
void Jit::Comp_RType3(MIPSOpcode op)
{
CONDITIONAL_DISABLE
CONDITIONAL_DISABLE(ALU);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -668,7 +668,7 @@ namespace MIPSComp
void Jit::Comp_ShiftType(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU);
int rs = (op>>21) & 0x1F;
MIPSGPReg rd = _RD;
int fd = (op>>6) & 0x1F;
@ -696,7 +696,7 @@ namespace MIPSComp
void Jit::Comp_Special3(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rs = _RS;
MIPSGPReg rt = _RT;
@ -786,7 +786,7 @@ namespace MIPSComp
void Jit::Comp_Allegrex(MIPSOpcode op)
{
CONDITIONAL_DISABLE
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rt = _RT;
MIPSGPReg rd = _RD;
// Don't change $zr.
@ -894,7 +894,7 @@ namespace MIPSComp
void Jit::Comp_Allegrex2(MIPSOpcode op)
{
CONDITIONAL_DISABLE
CONDITIONAL_DISABLE(ALU_BIT);
MIPSGPReg rt = _RT;
MIPSGPReg rd = _RD;
// Don't change $zr.
@ -938,7 +938,7 @@ namespace MIPSComp
void Jit::Comp_MulDivType(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(MULDIV);
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;

12
Core/MIPS/x86/CompFPU.cpp
View file

@ -42,7 +42,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp {
@ -86,7 +86,7 @@ void Jit::CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpAr
}
void Jit::Comp_FPU3op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU);
switch (op & 0x3f) {
case 0: CompFPTriArith(op, &XEmitter::ADDSS, false); break; //F(fd) = F(fs) + F(ft); //add
case 1: CompFPTriArith(op, &XEmitter::SUBSS, true); break; //F(fd) = F(fs) - F(ft); //sub
@ -99,7 +99,7 @@ void Jit::Comp_FPU3op(MIPSOpcode op) {
}
void Jit::Comp_FPULS(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_FPU);
s32 offset = _IMM16;
int ft = _FT;
MIPSGPReg rs = _RS;
@ -174,7 +174,7 @@ void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN) {
}
void Jit::Comp_FPUComp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU_COMP);
int fs = _FS;
int ft = _FT;
@ -226,7 +226,7 @@ void Jit::Comp_FPUComp(MIPSOpcode op) {
}
void Jit::Comp_FPU2op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU);
int fs = _FS;
int fd = _FD;
@ -355,7 +355,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
}
void Jit::Comp_mxc1(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(FPU_XFER);
int fs = _FS;
MIPSGPReg rt = _RT;

20
Core/MIPS/x86/CompLoadStore.cpp
View file

@ -42,7 +42,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { Comp_Generic(op); return; }
namespace MIPSComp {
@ -50,7 +50,7 @@ namespace MIPSComp {
void Jit::CompITypeMemRead(MIPSOpcode op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), const void *safeFunc)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
int offset = _IMM16;
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -81,7 +81,7 @@ namespace MIPSComp {
void Jit::CompITypeMemWrite(MIPSOpcode op, u32 bits, const void *safeFunc)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
int offset = _IMM16;
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -137,7 +137,7 @@ namespace MIPSComp {
void Jit::CompITypeMemUnpairedLR(MIPSOpcode op, bool isStore)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
int o = op>>26;
int offset = _IMM16;
MIPSGPReg rt = _RT;
@ -193,7 +193,7 @@ namespace MIPSComp {
void Jit::CompITypeMemUnpairedLRInner(MIPSOpcode op, X64Reg shiftReg)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
int o = op>>26;
MIPSGPReg rt = _RT;
@ -285,7 +285,7 @@ namespace MIPSComp {
void Jit::Comp_ITypeMem(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU);
int offset = _IMM16;
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
@ -334,7 +334,7 @@ namespace MIPSComp {
MIPSOpcode nextOp = GetOffsetInstruction(1);
// Looking for lwr rd, offset-3(rs) which makes a pair.
u32 desiredOp = ((op & 0xFFFF0000) + (4 << 26)) + (offset - 3);
if (!js.inDelaySlot && nextOp == desiredOp)
if (!js.inDelaySlot && nextOp == desiredOp && !jo.Disabled(JitDisable::LSU_UNALIGNED))
{
EatInstruction(nextOp);
// nextOp has the correct address.
@ -350,7 +350,7 @@ namespace MIPSComp {
MIPSOpcode nextOp = GetOffsetInstruction(1);
// Looking for lwl rd, offset+3(rs) which makes a pair.
u32 desiredOp = ((op & 0xFFFF0000) - (4 << 26)) + (offset + 3);
if (!js.inDelaySlot && nextOp == desiredOp)
if (!js.inDelaySlot && nextOp == desiredOp && !jo.Disabled(JitDisable::LSU_UNALIGNED))
{
EatInstruction(nextOp);
// op has the correct address.
@ -366,7 +366,7 @@ namespace MIPSComp {
MIPSOpcode nextOp = GetOffsetInstruction(1);
// Looking for swr rd, offset-3(rs) which makes a pair.
u32 desiredOp = ((op & 0xFFFF0000) + (4 << 26)) + (offset - 3);
if (!js.inDelaySlot && nextOp == desiredOp)
if (!js.inDelaySlot && nextOp == desiredOp && !jo.Disabled(JitDisable::LSU_UNALIGNED))
{
EatInstruction(nextOp);
// nextOp has the correct address.
@ -382,7 +382,7 @@ namespace MIPSComp {
MIPSOpcode nextOp = GetOffsetInstruction(1);
// Looking for swl rd, offset+3(rs) which makes a pair.
u32 desiredOp = ((op & 0xFFFF0000) - (4 << 26)) + (offset + 3);
if (!js.inDelaySlot && nextOp == desiredOp)
if (!js.inDelaySlot && nextOp == desiredOp && !jo.Disabled(JitDisable::LSU_UNALIGNED))
{
EatInstruction(nextOp);
// op has the correct address.

72
Core/MIPS/x86/CompVFPU.cpp
View file

@ -42,7 +42,7 @@
// Currently known non working ones should have DISABLE.
// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocks(); Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
#define DISABLE { fpr.ReleaseSpillLocks(); Comp_Generic(op); return; }
#define _RS MIPS_GET_RS(op)
@ -74,7 +74,7 @@ alignas(16) const float identityMatrix[4][4] = { { 1.0f, 0, 0, 0 }, { 0, 1.0f, 0
void Jit::Comp_VPFX(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int data = op & 0xFFFFF;
int regnum = (op >> 24) & 3;
switch (regnum) {
@ -239,7 +239,7 @@ bool IsOverlapSafe(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[]
alignas(16) static u32 ssLoadStoreTemp;
void Jit::Comp_SV(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
s32 imm = (signed short)(op&0xFFFC);
int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);
@ -294,7 +294,7 @@ void Jit::Comp_SV(MIPSOpcode op) {
}
void Jit::Comp_SVQ(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(LSU_VFPU);
int imm = (signed short)(op&0xFFFC);
int vt = (((op >> 16) & 0x1f)) | ((op&1) << 5);
@ -502,7 +502,7 @@ void Jit::Comp_SVQ(MIPSOpcode op) {
}
void Jit::Comp_VVectorInit(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -557,7 +557,7 @@ void Jit::Comp_VVectorInit(MIPSOpcode op) {
}
void Jit::Comp_VIdt(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -608,7 +608,7 @@ void Jit::Comp_VIdt(MIPSOpcode op) {
}
void Jit::Comp_VDot(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -739,7 +739,7 @@ void Jit::Comp_VDot(MIPSOpcode op) {
void Jit::Comp_VHdp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -788,7 +788,7 @@ void Jit::Comp_VHdp(MIPSOpcode op) {
}
void Jit::Comp_VCrossQuat(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -921,7 +921,7 @@ void Jit::Comp_VCrossQuat(MIPSOpcode op) {
}
void Jit::Comp_Vcmov(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix())
DISABLE;
@ -997,7 +997,7 @@ static s32 DoVmaxSS(s32 treg) {
}
void Jit::Comp_VecDo3(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1269,7 +1269,7 @@ alignas(16) static const u32 vcmpMask[4][4] = {
};
void Jit::Comp_Vcmp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_COMP);
if (js.HasUnknownPrefix())
DISABLE;
@ -1512,7 +1512,7 @@ extern const float mulTableVi2f[32] = {
};
void Jit::Comp_Vi2f(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1599,7 +1599,7 @@ void Jit::Comp_Vi2f(MIPSOpcode op) {
// Translation of ryg's half_to_float5_SSE2
void Jit::Comp_Vh2f(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1688,7 +1688,7 @@ alignas(16) static s8 vc2i_shuffle[16] = { -1, -1, -1, 0, -1, -1, -1, 1, -1, -
alignas(16) static s8 vuc2i_shuffle[16] = { 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3 };
void Jit::Comp_Vx2i(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1811,7 +1811,7 @@ static const float half = 0.5f;
static const double maxMinIntAsDouble[2] = { (double)0x7fffffff, (double)(int)0x80000000 }; // that's not equal to 0x80000000
void Jit::Comp_Vf2i(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -1920,7 +1920,7 @@ void Jit::Comp_Vf2i(MIPSOpcode op) {
}
void Jit::Comp_Vcst(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -1957,7 +1957,7 @@ void Jit::Comp_Vcst(MIPSOpcode op) {
}
void Jit::Comp_Vsgn(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -2018,7 +2018,7 @@ void Jit::Comp_Vsgn(MIPSOpcode op) {
}
void Jit::Comp_Vocp(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -2067,7 +2067,7 @@ void Jit::Comp_Vocp(MIPSOpcode op) {
}
void Jit::Comp_Vbfy(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -2181,7 +2181,7 @@ void SinCosNegSin(SinCosArg angle, float *output) {
}
void Jit::Comp_VV2Op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -2419,7 +2419,7 @@ void Jit::Comp_VV2Op(MIPSOpcode op) {
}
void Jit::Comp_Mftv(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int imm = op & 0xFF;
MIPSGPReg rt = _RT;
@ -2509,7 +2509,7 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
}
void Jit::Comp_Vmfvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int vs = _VS;
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
@ -2525,7 +2525,7 @@ void Jit::Comp_Vmfvc(MIPSOpcode op) {
}
void Jit::Comp_Vmtvc(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
int vs = _VS;
int imm = op & 0xFF;
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
@ -2549,7 +2549,7 @@ void Jit::Comp_Vmtvc(MIPSOpcode op) {
}
void Jit::Comp_VMatrixInit(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -2632,7 +2632,7 @@ void Jit::Comp_VMatrixInit(MIPSOpcode op) {
}
void Jit::Comp_Vmmov(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// TODO: This probably ignores prefixes?
if (js.HasUnknownPrefix())
@ -2718,7 +2718,7 @@ void Jit::Comp_Vmmov(MIPSOpcode op) {
}
void Jit::Comp_VScl(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -2780,7 +2780,7 @@ void Jit::Comp_VScl(MIPSOpcode op) {
}
void Jit::Comp_Vmmul(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// TODO: This probably ignores prefixes?
if (js.HasUnknownPrefix())
@ -2974,7 +2974,7 @@ void Jit::Comp_Vmmul(MIPSOpcode op) {
}
void Jit::Comp_Vmscl(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// TODO: This op probably ignores prefixes?
if (js.HasUnknownPrefix())
@ -3020,7 +3020,7 @@ void Jit::Comp_Vmscl(MIPSOpcode op) {
}
void Jit::Comp_Vtfm(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_MTX);
// TODO: This probably ignores prefixes? Or maybe uses D?
if (js.HasUnknownPrefix())
@ -3163,7 +3163,7 @@ alignas(16) static const s8 vi2xc_shuffle[16] = { 3, 7, 11, 15, -1, -1, -1, -1,
alignas(16) static const s8 vi2xs_shuffle[16] = { 2, 3, 6, 7, 10, 11, 14, 15, -1, -1, -1, -1, -1, -1, -1, -1 };
void Jit::Comp_Vi2x(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -3295,7 +3295,7 @@ void Jit::Comp_Vi2x(MIPSOpcode op) {
alignas(16) static const float vavg_table[4] = { 1.0f, 1.0f / 2.0f, 1.0f / 3.0f, 1.0f / 4.0f };
void Jit::Comp_Vhoriz(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;
@ -3412,7 +3412,7 @@ void Jit::Comp_Vhoriz(MIPSOpcode op) {
}
void Jit::Comp_Viim(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -3435,7 +3435,7 @@ void Jit::Comp_Viim(MIPSOpcode op) {
}
void Jit::Comp_Vfim(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_XFER);
if (js.HasUnknownPrefix())
DISABLE;
@ -3497,7 +3497,7 @@ void Jit::CompVrotShuffle(u8 *dregs, int imm, int n, bool negSin) {
// Very heavily used by FF:CC
void Jit::Comp_VRot(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix()) {
DISABLE;
}
@ -3569,7 +3569,7 @@ void Jit::Comp_VRot(MIPSOpcode op) {
}
void Jit::Comp_ColorConv(MIPSOpcode op) {
CONDITIONAL_DISABLE;
CONDITIONAL_DISABLE(VFPU_VEC);
if (js.HasUnknownPrefix())
DISABLE;