ppsspp/Core/MIPS/IR
Unknown W. Brackets ab809bd19e jit: Apply hasSetRounding at compile time.
Otherwise, the block will be executed with the wrong rounding mode the
first time rounding is set.  This could be important if it was set for a
single operation.

This is only a problem the first time it's set.
2018-04-01 10:36:16 -07:00
..
IRAsm.cpp Initial commit for IRJit 2016-05-07 13:58:29 +02:00
IRCompALU.cpp Minor cleanup 2018-01-10 09:19:27 +01:00
IRCompBranch.cpp irjit: Skip preloading blocks with jump to 0. 2018-01-06 17:23:53 -08:00
IRCompFPU.cpp Fix that weird unordered compare mode, hopefully 2018-01-04 20:06:26 +01:00
IRCompLoadStore.cpp irjit: Remove Comp_ITypeMemLR. 2018-01-09 18:06:25 -08:00
IRCompVFPU.cpp IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily. 2018-01-10 09:19:27 +01:00
IRFrontend.cpp jit: Apply hasSetRounding at compile time. 2018-04-01 10:36:16 -07:00
IRFrontend.h Minor cleanup 2018-01-10 09:19:27 +01:00
IRInst.cpp irjit: Add dedicated ops for lwl/swl and friends. 2018-01-07 21:05:57 -08:00
IRInst.h irjit: Add dedicated ops for lwl/swl and friends. 2018-01-07 21:05:57 -08:00
IRInterpreter.cpp irjit: Add dedicated ops for lwl/swl and friends. 2018-01-07 21:05:57 -08:00
IRInterpreter.h irjit: Embed constant inside IRInst. 2018-01-03 23:24:04 -08:00
IRJit.cpp arm64jit: Update rounding mode on thread switch. 2018-04-01 10:12:32 -07:00
IRJit.h arm64jit: Update rounding mode on thread switch. 2018-04-01 10:12:32 -07:00
IRPassSimplify.cpp irjit: Improve multiple lwr in a row. 2018-01-07 21:06:02 -08:00
IRPassSimplify.h irjit: Combine lwl/lwr and swl/swr, like before. 2018-01-07 21:05:58 -08:00
IRRegCache.cpp jit-ir: Less instructions cause flushing in constant propagation. 2016-05-08 23:25:08 +02:00
IRRegCache.h jit-ir: Less instructions cause flushing in constant propagation. 2016-05-08 23:25:08 +02:00