Emulation/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2025-04-02 11:01:50 -04:00
Code Issues Projects Releases Packages Wiki Activity
40100 commits 81 branches 122 tags 700 MiB
Commit graph

2798 commits

Author SHA1 Message Date
Henrik Rydgård
0e57cf30c7 ARM64: Disable the JIT implementation of the vh2f instruction, not accurate 2024-04-29 11:32:54 +02:00
Henrik Rydgård
814ba6ef44
Merge pull request #18973 from GermanAizek/fix-return-copies 
Fixed return copies from functions and added const ref params
 2024-04-03 00:21:48 +02:00
Herman Semenov
7b3c45508b Protect against undefined behavior when bitwise shift occurs with negative value 2024-04-02 19:31:04 +03:00
Herman Semenov
17ecee1715 Fixed return copies from functions and const ref params 2024-04-02 18:37:00 +03:00
Henrik Rydgård
22c9437319 Fix wrong timer reading in MIPSDebugInterface, thanks Nemoumbra 2024-03-26 13:40:25 +01:00
Henrik Rydgård
f73d0587d4 Comments, make locking more consistent in GameInfoCache 2024-01-19 14:56:29 +01:00
Henrik Rydgård
7e427e41d1 Remove a bunch of dead code from CoreTiming ("threadsafe" events) 
We haven't used these "threadsafe" events since we removed our first attempt
at GPU threading, so like 10 years, and maybe some experimentation in the
networking code according to some comments. It's unlikely that any
savestates that used these events would load anyway.
 2024-01-16 09:06:03 +01:00
Henrik Rydgård
3deabaeb04 JitBlockCache: Add a debug assert 2024-01-15 23:28:59 +01:00
Nemoumbra
f6c5edb725 Added function names from ULES00590 (Aces of War) 2024-01-10 03:04:29 +03:00
Henrik Rydgård
46b25d20a4
Merge pull request #18637 from unknownbrackets/riscv-more 
Add some more RISC-V extensions to emitter
 2023-12-29 19:03:49 +01:00
Henrik Rydgård
5c1767c849
Merge pull request #18636 from unknownbrackets/debug-log-usec 
Debugger: Add usec for breakpoint logging
 2023-12-29 18:58:23 +01:00
Unknown W. Brackets
15cb782f85 riscv: Implement Zfa encoding. 
Not yet enabled/detected.
 2023-12-29 09:42:23 -08:00
Unknown W. Brackets
ebf6f14a31 Debugger: Add usec for breakpoint logging. 2023-12-29 09:39:39 -08:00
Henrik Rydgård
e3177ac870 Make some global string pointers const, not just the strings. 
Minor cleanup.
 2023-12-29 14:09:45 +01:00
Henrik Rydgård
126d88ecfc Back out clearly inconsequential/useless .reserve() calls 2023-12-29 08:27:56 +01:00
Henrik Rydgård
dd1396e2fd
Merge pull request #18581 from GermanAizek/lower-scope 
Reduced lower scope for local objects
 2023-12-20 14:53:36 +01:00
Herman Semenov
2a31f8c6c0 [Common/Core/HLE] Object out of scope optimization for better codegeneration (lower level scope) 2023-12-20 12:33:56 +03:00
Henrik Rydgård
f2ee437323
Merge pull request #18579 from GermanAizek/emplace_back 
Minor replaced insert to emplace C++11
 2023-12-19 14:30:26 +01:00
Herman Semenov
4ea842a3c1 Minor replaced insert to emplace C++11 2023-12-19 16:06:48 +03:00
Henrik Rydgård
e5af1f8bd0
Merge pull request #18560 from unknownbrackets/replacement-slice 
HLE: Slice the very slow memset/memcpy variants
 2023-12-17 12:35:48 +01:00
Unknown W. Brackets
053831bf4d HLE: Add mechanics for sliced replacements. 2023-12-16 09:08:58 -08:00
Unknown W. Brackets
5311997753 x86jit: Correct downcount on replacement in IR. 2023-12-16 08:10:29 -08:00
Herman Semenov
b871e76d05 [Core/Debugger/FileLoaders/FileSystems/MIPS] Using reserve if possible 2023-12-15 13:59:19 +03:00
Henrik Rydgård
45aae7b9da ARM32: Backport a lot of previously 64-bit-only NEON optimizations to ARM32. 2023-11-27 23:51:10 +01:00
Henrik Rydgård
8ff38d0a9b
Merge pull request #18360 from unknownbrackets/arm64jit-fixes 
Fix some arm64jit issues
 2023-10-15 07:34:03 +02:00
Unknown W. Brackets
5e813e6bd6 irjit: Correct bad Vec4 overlap handling. 2023-10-14 20:54:40 -07:00
Unknown W. Brackets
2a24c99441 arm64jit: Correct FlushBeforeCall pairing. 
Oops, some silly mistakes here.
 2023-10-14 20:54:40 -07:00
Unknown W. Brackets
b85b0476b9 arm64jit: Correct vdot vec4 mapping. 2023-10-14 20:54:40 -07:00
Henrik Rydgård
64ee5675b8 Minor unrelated cleanup 2023-10-06 15:39:59 +02:00
Henrik Rydgård
0d06af87b6 Interpreter: Optimize ReadVector/WriteVector by removing voffset lookups 
Drops these functions down the ranking of top functions by quite a bit in GTA,
speedup at most 0.5% though. But enough of these small ones and they
start adding up.

Not sure why GTA falls back to the interpreter for these so much though.
I guess some "uneaten" prefix..
 2023-10-05 19:11:34 +02:00
Henrik Rydgård
60a304f29b Turn the ifs inside out 2023-10-05 18:59:56 +02:00
Henrik Rydgård
f21523ff74 WriteVector: Pluck transpose out of the loop 2023-10-05 18:56:15 +02:00
Henrik Rydgård
e852771480 Integrate the voffset shuffle in ReadVector 2023-10-05 18:52:50 +02:00
Henrik Rydgård
76f0c6cab4
Merge pull request #18305 from unknownbrackets/x86-ir-vcmp 
x86jit: Fix IR vcmp all bit
 2023-10-04 07:48:42 +02:00
Unknown W. Brackets
f1a9e39ce9 x86jit: Fix IR vcmp all bit. 2023-10-03 17:46:29 -07:00
Henrik Rydgård
7c184a7e1c
Merge pull request #18289 from fp64/sse2-vfpu-dot 
Add SSE2 version of vfpu_dot
 2023-10-03 10:39:10 +02:00
Unknown W. Brackets
521335cb2a x86: Fix 32-bit IR jit block entry. 2023-10-02 20:26:07 -07:00
fp64
49ac4c6774 Clarify 2023-10-02 14:05:49 -04:00
fp64
23e2d0f797 Add SSE2 version of vfpu_dot 
See #18249. Speedup for this function ranges 10%..100%,
depending on system. Updated verification and speed measurements:
https://godbolt.org/z/W1z3sj6hz
 2023-10-02 12:53:30 -04:00
Henrik Rydgård
db805cc4cc
Merge pull request #18282 from unknownbrackets/ir-compiling 
Improve IR compilation performance
 2023-10-01 11:34:27 +02:00
Henrik Rydgård
7bb7c2f28a
Merge pull request #18279 from unknownbrackets/arm64-ir-transfer 
arm64jit: Implement reg lane transfers in IR
 2023-10-01 11:31:19 +02:00
Unknown W. Brackets
cd46f0b4cb irjit: Cache IR metadata lookups. 
This improves compilation performance, because all those lookups were
adding up.
 2023-09-30 15:56:53 -07:00
Unknown W. Brackets
00c80cea6e irjit: Optimize offset logging during compile. 
As I guessed, this was expensive.  using a vector and reserve isn't very.
It's nice to keep this before logBlocks_ is > 0, in case it's set mid
block.
 2023-09-30 15:56:18 -07:00
Unknown W. Brackets
4e0761b104 irjit: Fix regcache disable for FPRs. 2023-09-30 15:54:54 -07:00
Unknown W. Brackets
4380bf9787 arm64jit: Optimize transfers to vec4 better. 2023-09-30 15:44:53 -07:00
Unknown W. Brackets
cb835295c8 arm64jit: Implement reg lane transfers. 2023-09-30 15:44:41 -07:00
Henrik Rydgård
5d8a0b3ac7
Merge pull request #18266 from unknownbrackets/ir-vtfm 
irjit: Fix vhtfm instruction
 2023-09-29 09:43:06 +02:00
Unknown W. Brackets
c92148ee2c irjit: Fix vhtfm instruction. 2023-09-28 21:16:54 -07:00
Henrik Rydgård
84d0236bf4 Comment fixes 2023-09-27 12:31:17 +02:00
Henrik Rydgård
4c0077fd84 Protect against weirdness in UnlinkBlocks (hopefully not needed after prev fix) 2023-09-27 12:31:17 +02:00