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https://github.com/hrydgard/ppsspp.git
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riscv: Implement Zfa encoding.
Not yet enabled/detected.
This commit is contained in:
Unknown W. Brackets
parent
ecb7f93418
commit
15cb782f85
6 changed files with 248 additions and 47 deletions
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@ -75,6 +75,11 @@ static inline bool SupportsFloatHalf(bool allowMin = false) {
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return false;
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}
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static inline bool SupportsFloatExtra() {
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// TODO: cpu_info.RiscV_Zfa
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return false;
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}
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enum class Opcode32 {
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// Note: invalid, just used for FixupBranch.
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ZERO = 0b0000000,
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@ -156,6 +161,8 @@ enum class Funct3 {
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FMIN = 0b000,
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FMAX = 0b001,
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FMINM = 0b010,
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FMAXM = 0b011,
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FMV = 0b000,
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FCLASS = 0b001,
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@ -2216,6 +2223,162 @@ void RiscVEmitter::FCLASS(int bits, RiscVReg rd, RiscVReg rs1) {
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Write32(EncodeR(Opcode32::OP_FP, rd, Funct3::FCLASS, rs1, F0, BitsToFunct2(bits), Funct5::FMV_TOX));
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}
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static const uint32_t FLIvalues[32] = {
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0xBF800000, // -1.0
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0x00800000, // FLT_MIN (note: a bit special)
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0x37800000, // pow(2, -16)
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0x38000000, // pow(2, -15)
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0x3B800000, // pow(2, -8)
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0x3C000000, // pow(2, -7)
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0x3D800000, // 0.0625
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0x3E000000, // 0.125
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0x3E800000, // 0.25
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0x3EA00000, // 0.3125
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0x3EC00000, // 0.375
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0x3EE00000, // 0.4375
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0x3F000000, // 0.5
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0x3F200000, // 0.625
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0x3F400000, // 0.75
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0x3F600000, // 0.875
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0x3F800000, // 1.0
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0x3FA00000, // 1.25
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0x3FC00000, // 1.5
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0x3FE00000, // 1.75
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0x40000000, // 2.0
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0x40200000, // 2.5
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0x40400000, // 3.0
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0x40800000, // 4.0
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0x41000000, // 8.0
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0x41800000, // 16.0
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0x43000000, // 128.0
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0x43800000, // 256.0
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0x47000000, // pow(2, 15)
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0x47800000, // pow(2, 16)
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0x7F800000, // INFINITY
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0x7FC00000, // NAN
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};
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static RiscVReg EncodeFLImm(int bits, double v) {
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float f = (float)v;
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int index = -1;
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for (size_t i = 0; i < ARRAY_SIZE(FLIvalues); ++i) {
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if (memcmp(&f, &FLIvalues[i], sizeof(float)) == 0) {
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index = (int)i;
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break;
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}
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}
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// For 16-bit, 2/3 are subnormal and 29 is not possible. Just avoid for now.
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if (index != -1 && index != 1 && (bits > 16 || (index != 2 && index != 3 && index != 29)))
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return (RiscVReg)index;
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if (bits == 64) {
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uint64_t dmin = 0x0010000000000000ULL;
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if (memcmp(&v, &dmin, 8) == 0)
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return F1;
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} else if (bits == 32 && index == 1) {
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return F1;
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} else if (bits == 16) {
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uint64_t hmin = 0x3F10000000000000ULL;
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if (memcmp(&v, &hmin, 8) == 0)
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return F1;
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}
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return INVALID_REG;
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}
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bool RiscVEmitter::CanFLI(int bits, double v) const {
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if (!SupportsFloatExtra())
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return false;
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if (bits == 16 && !SupportsFloatHalf())
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return false;
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if (bits > FloatBitsSupported())
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return false;
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return EncodeFLImm(bits, v) != INVALID_REG;
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}
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bool RiscVEmitter::CanFLI(int bits, uint32_t pattern) const {
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float f;
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memcpy(&f, &pattern, sizeof(f));
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return CanFLI(bits, f);
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}
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void RiscVEmitter::FLI(int bits, RiscVReg rd, double v) {
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_assert_msg_(SupportsFloatExtra(), "%s cannot be used without Zfa", __func__);
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_assert_msg_(bits <= FloatBitsSupported(), "FLI cannot be used for %d bits, only %d/%d supported", bits, BitsSupported(), FloatBitsSupported());
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_assert_msg_(IsFPR(rd), "%s rd of wrong type", __func__);
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RiscVReg imm = EncodeFLImm(bits, v);
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_assert_msg_(imm != INVALID_REG, "FLI with unsupported constant %f for %d bits", v, bits);
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Write32(EncodeR(Opcode32::OP_FP, rd, Funct3::FMV, imm, F1, BitsToFunct2(bits, false), Funct5::FMV_FROMX));
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}
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void RiscVEmitter::FLI(int bits, RiscVReg rd, uint32_t pattern) {
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float f;
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memcpy(&f, &pattern, sizeof(f));
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FLI(bits, rd, f);
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}
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void RiscVEmitter::FMINM(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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_assert_msg_(SupportsFloatExtra(), "%s cannot be used without Zfa", __func__);
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Write32(EncodeFR(Opcode32::OP_FP, rd, Funct3::FMINM, rs1, rs2, BitsToFunct2(bits), Funct5::FMINMAX));
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}
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void RiscVEmitter::FMAXM(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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_assert_msg_(SupportsFloatExtra(), "%s cannot be used without Zfa", __func__);
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Write32(EncodeFR(Opcode32::OP_FP, rd, Funct3::FMAXM, rs1, rs2, BitsToFunct2(bits), Funct5::FMINMAX));
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}
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void RiscVEmitter::FROUND(int bits, RiscVReg rd, RiscVReg rs1, Round rm) {
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_assert_msg_(SupportsFloatExtra(), "%s cannot be used without Zfa", __func__);
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_assert_msg_(bits <= FloatBitsSupported(), "FROUND for %d float bits, only %d supported", bits, FloatBitsSupported());
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_assert_msg_(IsFPR(rd), "%s rd of wrong type", __func__);
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_assert_msg_(IsFPR(rs1), "%s rs1 of wrong type", __func__);
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Funct2 toFmt = BitsToFunct2(bits, false);
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Write32(EncodeR(Opcode32::OP_FP, rd, (Funct3)rm, rs1, F4, toFmt, Funct5::FCVT_SZ));
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}
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void RiscVEmitter::QuickFLI(int bits, RiscVReg rd, double v, RiscVReg scratchReg) {
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if (CanFLI(bits, v)) {
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FLI(bits, rd, v);
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} else if (bits == 64) {
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LI(scratchReg, v);
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FMV(FMv::D, FMv::X, rd, scratchReg);
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} else if (bits <= 32) {
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QuickFLI(32, rd, (float)v, scratchReg);
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} else {
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_assert_msg_(false, "Unsupported QuickFLI bits");
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}
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}
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void RiscVEmitter::QuickFLI(int bits, RiscVReg rd, uint32_t pattern, RiscVReg scratchReg) {
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if (CanFLI(bits, pattern)) {
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FLI(bits, rd, pattern);
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} else if (bits == 32) {
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LI(scratchReg, (int32_t)pattern);
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FMV(FMv::W, FMv::X, rd, scratchReg);
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} else if (bits == 16) {
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LI(scratchReg, (int16_t)pattern);
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FMV(FMv::H, FMv::X, rd, scratchReg);
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} else {
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_assert_msg_(false, "Unsupported QuickFLI bits");
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}
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}
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void RiscVEmitter::QuickFLI(int bits, RiscVReg rd, float v, RiscVReg scratchReg) {
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if (CanFLI(bits, v)) {
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FLI(bits, rd, v);
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} else if (bits == 64) {
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QuickFLI(32, rd, (double)v, scratchReg);
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} else if (bits == 32) {
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LI(scratchReg, v);
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FMV(FMv::D, FMv::X, rd, scratchReg);
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} else {
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_assert_msg_(false, "Unsupported QuickFLI bits");
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}
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}
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void RiscVEmitter::CSRRW(RiscVReg rd, Csr csr, RiscVReg rs1) {
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_assert_msg_(SupportsZicsr(), "%s instruction not supported", __func__);
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_assert_msg_((u32)csr <= 0x00000FFF, "%s with invalid CSR number", __func__);
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@ -421,6 +421,26 @@ public:
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void FLE(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FCLASS(int bits, RiscVReg rd, RiscVReg rs1);
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// Additional floating point (Zfa.)
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bool CanFLI(int bits, double v) const;
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bool CanFLI(int bits, uint32_t pattern) const;
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bool CanFLI(int bits, float v) const {
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return CanFLI(bits, (double)v);
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}
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void FLI(int bits, RiscVReg rd, double v);
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void FLI(int bits, RiscVReg rd, uint32_t pattern);
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void FLI(int bits, RiscVReg rd, float v) {
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FLI(bits, rd, (double)v);
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}
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void FMINM(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FMAXM(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
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void FROUND(int bits, RiscVReg rd, RiscVReg rs1, Round rm = Round::DYNAMIC);
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// Convenience helper for FLI support.
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void QuickFLI(int bits, RiscVReg rd, double v, RiscVReg scratchReg);
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void QuickFLI(int bits, RiscVReg rd, uint32_t pattern, RiscVReg scratchReg);
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void QuickFLI(int bits, RiscVReg rd, float v, RiscVReg scratchReg);
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// Control state register manipulation.
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void CSRRW(RiscVReg rd, Csr csr, RiscVReg rs1);
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void CSRRS(RiscVReg rd, Csr csr, RiscVReg rs1);
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@ -246,8 +246,7 @@ void RiscVJitBackend::CompIR_FCvt(IRInst inst) {
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tempReg = regs_.MapWithFPRTemp(inst);
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// Prepare the multiplier.
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LI(SCRATCH1, 1UL << (inst.src2 & 0x1F));
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FCVT(FConv::S, FConv::WU, tempReg, SCRATCH1, rm);
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QuickFLI(32, tempReg, (float)(1UL << (inst.src2 & 0x1F)), SCRATCH1);
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FMUL(32, regs_.F(inst.dest), regs_.F(inst.src1), tempReg, rm);
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// NAN and clamping should all be correct.
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@ -264,8 +263,7 @@ void RiscVJitBackend::CompIR_FCvt(IRInst inst) {
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FCVT(FConv::S, FConv::W, regs_.F(inst.dest), SCRATCH1);
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// Pre-divide so we can avoid any actual divide.
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LI(SCRATCH1, 1.0f / (1UL << (inst.src2 & 0x1F)));
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FMV(FMv::W, FMv::X, tempReg, SCRATCH1);
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QuickFLI(32, tempReg, 1.0f / (1UL << (inst.src2 & 0x1F)), SCRATCH1);
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FMUL(32, regs_.F(inst.dest), regs_.F(inst.dest), tempReg);
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break;
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@ -292,8 +290,7 @@ void RiscVJitBackend::CompIR_FSat(IRInst inst) {
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FCVT(FConv::S, FConv::W, tempReg, R_ZERO);
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// FLE here is intentional to convert -0.0 to +0.0.
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FLE(32, SCRATCH1, regs_.F(inst.src1), tempReg);
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LI(SCRATCH2, 1.0f);
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FMV(FMv::W, FMv::X, tempReg, SCRATCH2);
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QuickFLI(32, tempReg, 1.0f, SCRATCH2);
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FLT(32, SCRATCH2, tempReg, regs_.F(inst.src1));
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skipLower = BEQ(SCRATCH1, R_ZERO);
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@ -315,8 +312,7 @@ void RiscVJitBackend::CompIR_FSat(IRInst inst) {
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FMV(32, regs_.F(inst.dest), regs_.F(inst.src1));
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// First, set SCRATCH1 = clamp to negative, SCRATCH2 = clamp to positive.
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LI(SCRATCH2, -1.0f);
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FMV(FMv::W, FMv::X, tempReg, SCRATCH2);
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QuickFLI(32, tempReg, -1.0f, SCRATCH2);
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FLT(32, SCRATCH1, regs_.F(inst.src1), tempReg);
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FNEG(32, tempReg, tempReg);
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FLT(32, SCRATCH2, tempReg, regs_.F(inst.src1));
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@ -621,8 +617,7 @@ void RiscVJitBackend::CompIR_FSpecial(IRInst inst) {
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FSQRT(32, regs_.F(inst.dest), regs_.F(inst.src1));
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// Ugh, we can't really avoid a temp here. Probably not worth a permanent one.
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LI(SCRATCH1, 1.0f);
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FMV(FMv::W, FMv::X, tempReg, SCRATCH1);
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QuickFLI(32, tempReg, 1.0f, SCRATCH1);
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FDIV(32, regs_.F(inst.dest), tempReg, regs_.F(inst.dest));
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break;
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@ -635,8 +630,7 @@ void RiscVJitBackend::CompIR_FSpecial(IRInst inst) {
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FDIV(32, regs_.F(inst.dest), regs_.F(inst.dest), regs_.F(inst.src1));
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} else {
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tempReg = regs_.MapWithFPRTemp(inst);
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LI(SCRATCH1, 1.0f);
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FMV(FMv::W, FMv::X, tempReg, SCRATCH1);
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QuickFLI(32, tempReg, 1.0f, SCRATCH1);
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FDIV(32, regs_.F(inst.dest), tempReg, regs_.F(inst.src1));
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}
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break;
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@ -50,14 +50,10 @@ void RiscVJitBackend::CompIR_Basic(IRInst inst) {
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case IROp::SetConstF:
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regs_.Map(inst);
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if (inst.constant == 0) {
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if (inst.constant == 0)
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FCVT(FConv::S, FConv::W, regs_.F(inst.dest), R_ZERO);
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} else {
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// TODO: In the future, could use FLI if it's approved.
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// Also, is FCVT faster?
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LI(SCRATCH1, (int32_t)inst.constant);
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FMV(FMv::W, FMv::X, regs_.F(inst.dest), SCRATCH1);
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}
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else
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QuickFLI(32, regs_.F(inst.dest), inst.constant, SCRATCH1);
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break;
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case IROp::Downcount:
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@ -54,56 +54,86 @@ void RiscVJitBackend::CompIR_VecAssign(IRInst inst) {
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break;
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case Vec4Init::AllONE:
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LI(SCRATCH1, 1.0f);
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FMV(FMv::W, FMv::X, regs_.F(inst.dest), SCRATCH1);
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for (int i = 1; i < 4; ++i)
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FMV(32, regs_.F(inst.dest + i), regs_.F(inst.dest));
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if (CanFLI(32, 1.0f)) {
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for (int i = 0; i < 4; ++i)
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FLI(32, regs_.F(inst.dest + i), 1.0f);
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} else {
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LI(SCRATCH1, 1.0f);
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FMV(FMv::W, FMv::X, regs_.F(inst.dest), SCRATCH1);
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for (int i = 1; i < 4; ++i)
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FMV(32, regs_.F(inst.dest + i), regs_.F(inst.dest));
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}
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break;
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case Vec4Init::AllMinusONE:
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LI(SCRATCH1, -1.0f);
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FMV(FMv::W, FMv::X, regs_.F(inst.dest), SCRATCH1);
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for (int i = 1; i < 4; ++i)
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FMV(32, regs_.F(inst.dest + i), regs_.F(inst.dest));
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if (CanFLI(32, -1.0f)) {
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for (int i = 0; i < 4; ++i)
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FLI(32, regs_.F(inst.dest + i), -1.0f);
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} else {
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LI(SCRATCH1, -1.0f);
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FMV(FMv::W, FMv::X, regs_.F(inst.dest), SCRATCH1);
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for (int i = 1; i < 4; ++i)
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FMV(32, regs_.F(inst.dest + i), regs_.F(inst.dest));
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}
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break;
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case Vec4Init::Set_1000:
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LI(SCRATCH1, 1.0f);
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if (!CanFLI(32, 1.0f))
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LI(SCRATCH1, 1.0f);
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for (int i = 0; i < 4; ++i) {
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if (i == 0)
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FMV(FMv::W, FMv::X, regs_.F(inst.dest + i), SCRATCH1);
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else
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if (i == 0) {
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if (CanFLI(32, 1.0f))
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FLI(32, regs_.F(inst.dest + i), 1.0f);
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else
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FMV(FMv::W, FMv::X, regs_.F(inst.dest + i), SCRATCH1);
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} else {
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FCVT(FConv::S, FConv::W, regs_.F(inst.dest + i), R_ZERO);
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}
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}
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break;
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case Vec4Init::Set_0100:
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LI(SCRATCH1, 1.0f);
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if (!CanFLI(32, 1.0f))
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LI(SCRATCH1, 1.0f);
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for (int i = 0; i < 4; ++i) {
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if (i == 1)
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FMV(FMv::W, FMv::X, regs_.F(inst.dest + i), SCRATCH1);
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else
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if (i == 1) {
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if (CanFLI(32, 1.0f))
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FLI(32, regs_.F(inst.dest + i), 1.0f);
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else
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FMV(FMv::W, FMv::X, regs_.F(inst.dest + i), SCRATCH1);
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} else {
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FCVT(FConv::S, FConv::W, regs_.F(inst.dest + i), R_ZERO);
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}
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}
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break;
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case Vec4Init::Set_0010:
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LI(SCRATCH1, 1.0f);
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if (!CanFLI(32, 1.0f))
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LI(SCRATCH1, 1.0f);
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for (int i = 0; i < 4; ++i) {
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if (i == 2)
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FMV(FMv::W, FMv::X, regs_.F(inst.dest + i), SCRATCH1);
|
||||
else
|
||||
if (i == 2) {
|
||||
if (CanFLI(32, 1.0f))
|
||||
FLI(32, regs_.F(inst.dest + i), 1.0f);
|
||||
else
|
||||
FMV(FMv::W, FMv::X, regs_.F(inst.dest + i), SCRATCH1);
|
||||
} else {
|
||||
FCVT(FConv::S, FConv::W, regs_.F(inst.dest + i), R_ZERO);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case Vec4Init::Set_0001:
|
||||
LI(SCRATCH1, 1.0f);
|
||||
if (!CanFLI(32, 1.0f))
|
||||
LI(SCRATCH1, 1.0f);
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
if (i == 3)
|
||||
FMV(FMv::W, FMv::X, regs_.F(inst.dest + i), SCRATCH1);
|
||||
else
|
||||
if (i == 3) {
|
||||
if (CanFLI(32, 1.0f))
|
||||
FLI(32, regs_.F(inst.dest + i), 1.0f);
|
||||
else
|
||||
FMV(FMv::W, FMv::X, regs_.F(inst.dest + i), SCRATCH1);
|
||||
} else {
|
||||
FCVT(FConv::S, FConv::W, regs_.F(inst.dest + i), R_ZERO);
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -223,10 +223,8 @@ JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec, int
|
|||
}
|
||||
|
||||
// TODO: Only load these when needed?
|
||||
LI(scratchReg, by128);
|
||||
FMV(FMv::W, FMv::X, by128Reg, scratchReg);
|
||||
LI(scratchReg, by32768);
|
||||
FMV(FMv::W, FMv::X, by32768Reg, scratchReg);
|
||||
QuickFLI(32, by128Reg, by128, scratchReg);
|
||||
QuickFLI(32, by32768Reg, by32768, scratchReg);
|
||||
if (posThroughStep) {
|
||||
LI(scratchReg, const65535);
|
||||
FMV(FMv::W, FMv::X, const65535Reg, scratchReg);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue