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Merge pull request #18279 from unknownbrackets/arm64-ir-transfer
arm64jit: Implement reg lane transfers in IR
This commit is contained in:
Henrik Rydgård
GitHub
commit
7bb7c2f28a
2 changed files with 293 additions and 0 deletions
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@ -433,6 +433,295 @@ void Arm64IRRegCache::StoreRegValue(IRReg mreg, uint32_t imm) {
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emit_->STR(INDEX_UNSIGNED, storeReg, CTXREG, GetMipsRegOffset(mreg));
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}
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bool Arm64IRRegCache::TransferNativeReg(IRNativeReg nreg, IRNativeReg dest, MIPSLoc type, IRReg first, int lanes, MIPSMap flags) {
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bool allowed = !mr[nr[nreg].mipsReg].isStatic;
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// There's currently no support for non-FREGs here.
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allowed = allowed && type == MIPSLoc::FREG;
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if (dest == -1)
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dest = nreg;
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if (allowed && (flags == MIPSMap::INIT || flags == MIPSMap::DIRTY)) {
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// Alright, changing lane count (possibly including lane position.)
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IRReg oldfirst = nr[nreg].mipsReg;
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int oldlanes = 0;
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while (mr[oldfirst + oldlanes].nReg == nreg)
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oldlanes++;
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_assert_msg_(oldlanes != 0, "TransferNativeReg encountered nreg mismatch");
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_assert_msg_(oldlanes != lanes, "TransferNativeReg transfer to same lanecount, misaligned?");
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if (lanes == 1 && TransferVecTo1(nreg, dest, first, oldlanes))
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return true;
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if (oldlanes == 1 && Transfer1ToVec(nreg, dest, first, lanes))
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return true;
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}
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return IRNativeRegCacheBase::TransferNativeReg(nreg, dest, type, first, lanes, flags);
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}
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bool Arm64IRRegCache::TransferVecTo1(IRNativeReg nreg, IRNativeReg dest, IRReg first, int oldlanes) {
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IRReg oldfirst = nr[nreg].mipsReg;
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// Is it worth preserving any of the old regs?
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int numKept = 0;
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for (int i = 0; i < oldlanes; ++i) {
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// Skip whichever one this is extracting.
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if (oldfirst + i == first)
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continue;
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// If 0 isn't being transfered, easy to keep in its original reg.
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if (i == 0 && dest != nreg) {
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numKept++;
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continue;
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}
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IRNativeReg freeReg = FindFreeReg(MIPSLoc::FREG, MIPSMap::INIT);
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if (freeReg != -1 && IsRegRead(MIPSLoc::FREG, oldfirst + i)) {
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// If there's one free, use it. Don't modify nreg, though.
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fp_->DUP(32, FromNativeReg(freeReg), FromNativeReg(nreg), i);
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// Update accounting.
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nr[freeReg].isDirty = nr[nreg].isDirty;
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nr[freeReg].mipsReg = oldfirst + i;
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mr[oldfirst + i].lane = -1;
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mr[oldfirst + i].nReg = freeReg;
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numKept++;
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}
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}
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// Unless all other lanes were kept, store.
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if (nr[nreg].isDirty && numKept < oldlanes - 1) {
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StoreNativeReg(nreg, oldfirst, oldlanes);
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// Set false even for regs that were split out, since they were flushed too.
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for (int i = 0; i < oldlanes; ++i) {
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if (mr[oldfirst + i].nReg != -1)
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nr[mr[oldfirst + i].nReg].isDirty = false;
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}
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}
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// Next, move the desired element into first place.
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if (mr[first].lane > 0) {
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fp_->DUP(32, FromNativeReg(dest), FromNativeReg(nreg), mr[first].lane);
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} else if (mr[first].lane <= 0 && dest != nreg) {
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fp_->DUP(32, FromNativeReg(dest), FromNativeReg(nreg), 0);
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}
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// Now update accounting.
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for (int i = 0; i < oldlanes; ++i) {
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auto &mreg = mr[oldfirst + i];
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if (oldfirst + i == first) {
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mreg.lane = -1;
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mreg.nReg = dest;
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} else if (mreg.nReg == nreg && i == 0 && nreg != dest) {
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// Still in the same register, but no longer a vec.
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mreg.lane = -1;
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} else if (mreg.nReg == nreg) {
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// No longer in a register.
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mreg.nReg = -1;
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mreg.lane = -1;
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mreg.loc = MIPSLoc::MEM;
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}
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}
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if (dest != nreg) {
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nr[dest].isDirty = nr[nreg].isDirty;
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if (oldfirst == first) {
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nr[nreg].mipsReg = -1;
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nr[nreg].isDirty = false;
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}
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}
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nr[dest].mipsReg = first;
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return true;
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}
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bool Arm64IRRegCache::Transfer1ToVec(IRNativeReg nreg, IRNativeReg dest, IRReg first, int lanes) {
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ARM64Reg destReg = FromNativeReg(dest);
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ARM64Reg cur[4]{};
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int numInRegs = 0;
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u8 blendMask = 0;
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for (int i = 0; i < lanes; ++i) {
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if (mr[first + i].lane != -1 || (i != 0 && mr[first + i].spillLockIRIndex >= irIndex_)) {
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// Can't do it, either double mapped or overlapping vec.
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return false;
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}
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if (mr[first + i].nReg == -1) {
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cur[i] = INVALID_REG;
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blendMask |= 1 << i;
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} else {
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cur[i] = FromNativeReg(mr[first + i].nReg);
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numInRegs++;
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}
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}
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// Shouldn't happen, this should only get called to transfer one in a reg.
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if (numInRegs == 0)
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return false;
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// If everything's currently in a reg, move it into this reg.
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if (lanes == 4) {
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// Go with an exhaustive approach, only 15 possibilities...
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if (blendMask == 0) {
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// y = yw##, x = xz##, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[3]));
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fp_->ZIP1(32, EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[2]));
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fp_->ZIP1(32, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[1]));
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} else if (blendMask == 0b0001) {
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// y = yw##, w = x###, w = xz##, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[3]));
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fp_->LDR(32, INDEX_UNSIGNED, cur[3], CTXREG, GetMipsRegOffset(first + 0));
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fp_->ZIP1(32, EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[2]));
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fp_->ZIP1(32, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[1]));
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} else if (blendMask == 0b0010) {
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// x = xz##, z = y###, z = yw##, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[2]));
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fp_->LDR(32, INDEX_UNSIGNED, cur[2], CTXREG, GetMipsRegOffset(first + 1));
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fp_->ZIP1(32, EncodeRegToQuad(cur[2]), EncodeRegToQuad(cur[2]), EncodeRegToQuad(cur[3]));
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fp_->ZIP1(32, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[2]));
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} else if (blendMask == 0b0011 && (first & 1) == 0) {
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// z = zw##, w = xy##, dest = xyzw. Mixed lane sizes.
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fp_->ZIP1(32, EncodeRegToQuad(cur[2]), EncodeRegToQuad(cur[2]), EncodeRegToQuad(cur[3]));
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fp_->LDR(64, INDEX_UNSIGNED, EncodeRegToDouble(cur[3]), CTXREG, GetMipsRegOffset(first + 0));
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fp_->ZIP1(64, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[2]));
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} else if (blendMask == 0b0100) {
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// y = yw##, w = z###, x = xz##, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[3]));
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fp_->LDR(32, INDEX_UNSIGNED, cur[3], CTXREG, GetMipsRegOffset(first + 2));
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fp_->ZIP1(32, EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[3]));
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fp_->ZIP1(32, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[1]));
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} else if (blendMask == 0b0101 && (first & 3) == 0) {
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// y = yw##, w=x#z#, w = xz##, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[3]));
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(cur[3]), CTXREG, GetMipsRegOffset(first));
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fp_->UZP1(32, EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[3]));
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fp_->ZIP1(32, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[1]));
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} else if (blendMask == 0b0110 && (first & 3) == 0) {
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if (destReg == cur[0]) {
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// w = wx##, dest = #yz#, dest = xyz#, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[3]), EncodeRegToQuad(cur[0]));
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 0, EncodeRegToQuad(cur[3]), 1);
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fp_->INS(32, EncodeRegToQuad(destReg), 3, EncodeRegToQuad(cur[3]), 0);
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} else {
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// Assumes destReg may equal cur[3].
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// x = xw##, dest = #yz#, dest = xyz#, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[3]));
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 0, EncodeRegToQuad(cur[0]), 0);
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fp_->INS(32, EncodeRegToQuad(destReg), 3, EncodeRegToQuad(cur[0]), 1);
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}
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} else if (blendMask == 0b0111 && (first & 3) == 0 && destReg != cur[3]) {
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// dest = xyz#, dest = xyzw.
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 3, EncodeRegToQuad(cur[3]), 0);
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} else if (blendMask == 0b1000) {
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// x = xz##, z = w###, y = yw##, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[2]));
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fp_->LDR(32, INDEX_UNSIGNED, cur[2], CTXREG, GetMipsRegOffset(first + 3));
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fp_->ZIP1(32, EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[2]));
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fp_->ZIP1(32, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[1]));
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} else if (blendMask == 0b1001 && (first & 3) == 0) {
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if (destReg == cur[1]) {
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// w = zy##, dest = x##w, dest = xy#w, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[2]), EncodeRegToQuad(cur[2]), EncodeRegToQuad(cur[1]));
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 1, EncodeRegToQuad(cur[2]), 1);
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fp_->INS(32, EncodeRegToQuad(destReg), 2, EncodeRegToQuad(cur[2]), 0);
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} else {
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// Assumes destReg may equal cur[2].
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// y = yz##, dest = x##w, dest = xy#w, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[1]), EncodeRegToQuad(cur[2]));
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 1, EncodeRegToQuad(cur[1]), 0);
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fp_->INS(32, EncodeRegToQuad(destReg), 2, EncodeRegToQuad(cur[1]), 1);
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}
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} else if (blendMask == 0b1010 && (first & 3) == 0) {
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// x = xz##, z = #y#w, z=yw##, dest = xyzw.
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fp_->ZIP1(32, EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[2]));
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(cur[2]), CTXREG, GetMipsRegOffset(first));
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fp_->UZP2(32, EncodeRegToQuad(cur[2]), EncodeRegToQuad(cur[2]), EncodeRegToQuad(cur[2]));
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fp_->ZIP1(32, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[2]));
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} else if (blendMask == 0b1011 && (first & 3) == 0 && destReg != cur[2]) {
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// dest = xy#w, dest = xyzw.
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 2, EncodeRegToQuad(cur[2]), 0);
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} else if (blendMask == 0b1100 && (first & 1) == 0) {
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// x = xy##, y = zw##, dest = xyzw. Mixed lane sizes.
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fp_->ZIP1(32, EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[1]));
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fp_->LDR(64, INDEX_UNSIGNED, EncodeRegToDouble(cur[1]), CTXREG, GetMipsRegOffset(first + 2));
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fp_->ZIP1(64, EncodeRegToQuad(destReg), EncodeRegToQuad(cur[0]), EncodeRegToQuad(cur[1]));
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} else if (blendMask == 0b1101 && (first & 3) == 0 && destReg != cur[1]) {
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// dest = x#zw, dest = xyzw.
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 1, EncodeRegToQuad(cur[1]), 0);
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} else if (blendMask == 0b1110 && (first & 3) == 0 && destReg != cur[0]) {
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// dest = #yzw, dest = xyzw.
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 0, EncodeRegToQuad(cur[0]), 0);
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} else if (blendMask == 0b1110 && (first & 3) == 0) {
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// If dest == cur[0] (which may be common), we need a temp...
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IRNativeReg freeReg = FindFreeReg(MIPSLoc::FREG, MIPSMap::INIT);
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// Very unfortunate.
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if (freeReg == INVALID_REG)
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return false;
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// free = x###, dest = #yzw, dest = xyzw.
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fp_->DUP(32, EncodeRegToQuad(FromNativeReg(freeReg)), EncodeRegToQuad(cur[0]), 0);
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fp_->LDR(128, INDEX_UNSIGNED, EncodeRegToQuad(destReg), CTXREG, GetMipsRegOffset(first));
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fp_->INS(32, EncodeRegToQuad(destReg), 0, EncodeRegToQuad(FromNativeReg(freeReg)), 0);
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} else {
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return false;
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}
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} else if (lanes == 2) {
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if (cur[0] != INVALID_REG && cur[1] != INVALID_REG) {
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fp_->ZIP1(32, EncodeRegToDouble(destReg), EncodeRegToDouble(cur[0]), EncodeRegToDouble(cur[1]));
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} else if (cur[0] == INVALID_REG && dest != nreg) {
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fp_->LDR(32, INDEX_UNSIGNED, destReg, CTXREG, GetMipsRegOffset(first + 0));
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fp_->INS(32, EncodeRegToDouble(destReg), 1, EncodeRegToDouble(cur[1]), 0);
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} else {
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IRNativeReg freeReg = FindFreeReg(MIPSLoc::FREG, MIPSMap::INIT);
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if (freeReg == INVALID_REG)
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return false;
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if (cur[0] == INVALID_REG) {
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fp_->LDR(32, INDEX_UNSIGNED, FromNativeReg(freeReg), CTXREG, GetMipsRegOffset(first + 0));
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fp_->ZIP1(32, EncodeRegToDouble(destReg), EncodeRegToDouble(FromNativeReg(freeReg)), EncodeRegToDouble(cur[1]));
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} else {
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fp_->LDR(32, INDEX_UNSIGNED, FromNativeReg(freeReg), CTXREG, GetMipsRegOffset(first + 1));
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fp_->ZIP1(32, EncodeRegToDouble(destReg), EncodeRegToDouble(cur[0]), EncodeRegToDouble(FromNativeReg(freeReg)));
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}
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}
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} else {
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return false;
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}
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mr[first].lane = 0;
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for (int i = 0; i < lanes; ++i) {
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if (mr[first + i].nReg != -1) {
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// If this was dirty, the combined reg is now dirty.
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if (nr[mr[first + i].nReg].isDirty)
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nr[dest].isDirty = true;
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// Throw away the other register we're no longer using.
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if (i != 0)
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DiscardNativeReg(mr[first + i].nReg);
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}
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// And set it as using the new one.
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mr[first + i].lane = i;
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mr[first + i].loc = MIPSLoc::FREG;
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mr[first + i].nReg = dest;
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}
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if (dest != nreg) {
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nr[dest].mipsReg = first;
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nr[nreg].mipsReg = -1;
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nr[nreg].isDirty = false;
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}
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return true;
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}
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void Arm64IRRegCache::FlushAll(bool gprs, bool fprs) {
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// Note: make sure not to change the registers when flushing:
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// Branching code may expect the armreg to retain its value.
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@ -91,8 +91,12 @@ protected:
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void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void SetNativeRegValue(IRNativeReg nreg, uint32_t imm) override;
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void StoreRegValue(IRReg mreg, uint32_t imm) override;
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bool TransferNativeReg(IRNativeReg nreg, IRNativeReg dest, MIPSLoc type, IRReg first, int lanes, MIPSMap flags) override;
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private:
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bool TransferVecTo1(IRNativeReg nreg, IRNativeReg dest, IRReg first, int oldlanes);
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bool Transfer1ToVec(IRNativeReg nreg, IRNativeReg dest, IRReg first, int lanes);
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IRNativeReg GPRToNativeReg(Arm64Gen::ARM64Reg r);
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IRNativeReg VFPToNativeReg(Arm64Gen::ARM64Reg r);
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Arm64Gen::ARM64Reg FromNativeReg(IRNativeReg r);
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