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40100 commits 81 branches 122 tags 700 MiB
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41 commits

Author SHA1 Message Date
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15cb782f85 riscv: Implement Zfa encoding. 
Not yet enabled/detected.
 2023-12-29 09:42:23 -08:00
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9b2fa46861 IR: Add mini native jit MIPS block profiler. 2023-09-24 23:04:29 -07:00
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14e2e1ed62 x64jit: Optimize FCmpVfpuAggregate. 2023-09-23 14:31:46 -07:00
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7a5cdafdf3 arm64jit: Implement convert/int conversions. 2023-09-08 00:03:12 -07:00
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a1304f6ac8 arm64jit: Implement VFPU compare in IR. 2023-09-06 19:02:24 -07:00
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97d9a7f07f arm64jit: Implement FCmp. 2023-09-06 00:09:26 -07:00
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61a99b4bac x86jit: Implement trig/reciprocals. 2023-08-27 23:24:30 -07:00
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4b1c809886 x86jit: Implement a few more float ops, shuffle. 2023-08-27 23:24:30 -07:00
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4e3f3860f9 x86jit: Stub out op categories to files. 2023-08-20 22:28:54 -07:00
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6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
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a190793ad2 riscv: Simplify mapping for more instructions. 2023-08-20 12:42:11 -07:00
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e40ae60029 riscv: Mark normalized32 after mapping. 
It's less confusing to separate it.
 2023-08-20 12:42:11 -07:00
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f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
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a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
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4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
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b30daa5760 riscv: Centralize state of regcaches. 2023-08-15 21:51:38 -07:00
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be938a850b riscv: Remove FMul safety check. 
Let's just see if everything's right, this bloats multiplies a lot.
Doesn't seem to impact perf a lot, though.
 2023-08-13 10:20:20 -07:00
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4b9011e475 riscv: Reduce call bloat using temps. 2023-08-08 23:17:32 -07:00
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268adf1aa1 riscv: Implement scaled float/int convert. 2023-08-08 23:17:32 -07:00
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93e3d35f5d irjit: Move more to IRNativeBackend, split. 2023-08-06 00:16:43 -07:00
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b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit 
riscv: Spill registers more intelligently
 2023-07-30 14:49:37 -07:00
Henrik Rydgård
fa558b5b71
Merge pull request #17813 from unknownbrackets/riscv-jit-fixes 
Fix some typos and mistakes in RISC-V jit
 2023-07-30 23:41:13 +02:00
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020706f545 riscv: Implement float saturate clamping. 2023-07-30 14:24:12 -07:00
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09f3842a32 riscv: Fix VFPU compare typos. 2023-07-30 14:19:28 -07:00
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5db6b11ef2 irjit: Cleanup self-fmovs. 
These were sometimes getting emitted.
 2023-07-30 14:16:17 -07:00
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26a527bdf8 riscv: Implement float/int conversion. 2023-07-30 00:45:51 -07:00
Henrik Rydgård
b93275bb35
Merge pull request #17800 from unknownbrackets/riscv-jit 
More RISC-V jit ops
 2023-07-30 09:26:22 +02:00
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0036f3c494 riscv: Implement FMin/FMax. 2023-07-30 00:02:10 -07:00
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8e8081c686 riscv: Implement VFPU compares. 2023-07-30 00:02:10 -07:00
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9c9330a207 riscv: Implement float conditional move. 2023-07-30 00:02:10 -07:00
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6d4fb949c2 riscv: Implement float compare ops. 2023-07-29 19:02:15 -07:00
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6b632a103d riscv: Implement FSin/similar. 2023-07-29 19:02:15 -07:00
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e228748449 irjit: Add FCvtScaledSW to safely scale vi2f. 2023-07-29 18:30:15 -07:00
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a5a2671af3 irjit: Implement vf2ix. 
Used in LittleBigPlanet when playing intro movies.
 2023-07-29 18:01:08 -07:00
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a181f6d5b8 riscv: Add a comment for FMUL testing later. 2023-07-27 22:16:29 -07:00
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ca7a520a19 riscv: Implement FMul. 2023-07-25 20:33:56 -07:00
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9a9b371856 riscv: Implement FSign using FCLASS. 2023-07-25 20:33:56 -07:00
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05360d5c7a riscv: Implement simplest float ops. 2023-07-25 20:33:56 -07:00
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7071884a47 riscv: Handle rounding mode and ctrl transfers. 2023-07-25 20:33:56 -07:00
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c2da7d18bb riscv: Stub out more IR compilation categories. 2023-07-23 18:01:00 -07:00
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bf7a6eb2cd riscv: Add jit for some initial instructions. 2023-07-23 18:01:00 -07:00