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riscv: Implement FMul.

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Unknown W. Brackets 2023-07-24 22:59:08 -07:00
parent 9a9b371856
commit ca7a520a19
1 changed files with 29 additions and 1 deletions
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30
Core/MIPS/RiscV/RiscVCompFPU.cpp
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@ -51,7 +51,35 @@ void RiscVJit::CompIR_FArith(IRInst inst) {
case IROp::FMul:
fpr.MapDirtyInIn(inst.dest, inst.src1, inst.src2);
if (inst.src1 != inst.src2) {
CompIR_Generic(inst);
// These will output 0x80/0x01 if infinity, 0x10/0x80 if zero.
// We need to check if one is infinity and the other zero.
// First, try inf * zero.
FCLASS(32, SCRATCH1, fpr.R(inst.src1));
FCLASS(32, SCRATCH2, fpr.R(inst.src2));
ANDI(R_RA, SCRATCH1, 0x81);
FixupBranch lhsNotInf = BEQ(R_RA, R_ZERO);
ANDI(R_RA, SCRATCH2, 0x18);
FixupBranch infZero = BNE(R_RA, R_ZERO);
// Okay, what about the other order?
SetJumpTarget(lhsNotInf);
ANDI(R_RA, SCRATCH1, 0x18);
FixupBranch lhsNotZero = BEQ(R_RA, R_ZERO);
ANDI(R_RA, SCRATCH2, 0x81);
FixupBranch zeroInf = BNE(R_RA, R_ZERO);
// Nope, all good.
SetJumpTarget(lhsNotZero);
FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
FixupBranch skip = J();
SetJumpTarget(infZero);
SetJumpTarget(zeroInf);
LI(SCRATCH1, 0x7FC00000);
FMV(FMv::W, FMv::X, fpr.R(inst.dest), SCRATCH1);
SetJumpTarget(skip);
} else {
FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
}