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Author	SHA1	Message	Date
Paul Holden	3fab2afa55	Implement VSUM (also 'vec zero' op).	2023-09-23 22:17:55 +01:00
Paul Holden	1f1c0c99ea	Implement VADDB, VACCB, VSUCB, VSAD, VSAC (all 'vec zero' ops).	2023-09-23 22:17:55 +01:00
Paul Holden	95a13596d1	Implement VADDC.	2023-09-23 22:17:55 +01:00
Paul Holden	c93e106158	Implement VSUB, VSUT, VSUBC, VSUBB.	2023-09-23 22:17:55 +01:00
Paul Holden	84729a0ca1	Implement VMULU, VRNDP, VMULQ, VMUDL, VMUDM, VMUDN, VMADL, VMADM, VMADH.	2023-09-23 22:17:55 +01:00
Paul Holden	29c44a2ab8	Fix VRNDP disassembly.	2023-09-23 22:17:55 +01:00
Paul Holden	68da2313dd	Tidy	2023-09-23 22:17:55 +01:00
Paul Holden	3585965798	Implement VMULF.	2023-09-23 22:17:55 +01:00
Paul Holden	7e75c11f3b	Increase safety limit.	2023-09-23 22:17:55 +01:00
Paul Holden	684e45342b	Implement VMUDH, VMADN, VADD, VSAR.	2023-09-23 22:17:55 +01:00
Paul Holden	4e09435618	Add disassembly for some vector ops.	2023-09-23 22:17:55 +01:00
Paul Holden	61df6d685f	Fix cop2 instruction decode.	2023-09-23 22:17:55 +01:00
Paul Holden	c37c1507e0	Make the temp vector general purpose.	2023-09-23 22:17:55 +01:00
Paul Holden	3b3ae6fd3e	Split up opcode for LWC2/SWC2 and COP2. ... They have a different encoding for 'e' or 'element' which is likely to get confusing.	2023-09-23 22:17:55 +01:00
Paul Holden	21703641f9	Implement LTV.	2023-09-23 22:17:55 +01:00
Paul Holden	632c3c5ae2	Implement LFV.	2023-09-23 22:17:55 +01:00
Paul Holden	09f6ead752	Implement LPV, LUV, LHV.	2023-09-23 22:17:55 +01:00
Paul Holden	bc3e6c5053	Implement LPV.	2023-09-23 22:17:55 +01:00
Paul Holden	d486afe780	Fix LQV and SQV at end of dmem.	2023-09-23 22:17:55 +01:00
Paul Holden	5f9a989197	Implement MFC2 and MTC2.	2023-09-23 22:17:55 +01:00
Paul Holden	f7864fa0bf	Implement CFC2/CTC2.	2023-09-23 22:17:55 +01:00
Paul Holden	0a0e0b7b72	Fix CFC2/CTC2 disassembly - reg 3 is treated as VCE.	2023-09-23 22:17:55 +01:00
Paul Holden	a1ab3c2bb9	Tidy comment.	2023-09-23 22:17:55 +01:00
Paul Holden	5bd3dd9412	Implement STV.	2023-09-23 22:17:55 +01:00
Paul Holden	3bfb13c20c	Assert element index is in bounds.	2023-09-23 22:17:55 +01:00
Paul Holden	75682a99d4	Implement SWV.	2023-09-23 22:17:55 +01:00
Paul Holden	6a20c7cb1d	Implement SFV.	2023-09-23 22:17:55 +01:00
Paul Holden	967215a633	Implement SPV, SUV and SHV.	2023-09-23 22:17:55 +01:00
Paul Holden	e4fc415ba6	Stores should wrap.	2023-09-23 22:17:55 +01:00
Paul Holden	5dd4e6d6ec	Tidy	2023-09-23 22:17:55 +01:00
Paul Holden	a35a105c0e	Implement LBV, LSV, LLV, LDV, LQV, LRV, SBV, SSV, SLV, SDV, SQV, SRV.	2023-09-23 22:17:55 +01:00
Paul Holden	f885bf9441	Fix disassembly for vector stores and loads.	2023-09-23 22:17:55 +01:00
Paul Holden	20fd66a359	Add some missing vector ops.	2023-09-23 22:17:55 +01:00
Paul Holden	1091bce4aa	Initial RSP implementation.	2023-09-23 22:17:55 +01:00
Paul Holden	e5f3c8c7d2	Split out writeReg so it can be called from the RSP.	2023-09-23 22:17:55 +01:00
Paul Holden	107763f3be	Include the address in the disassembly.	2023-09-23 22:17:55 +01:00
Paul Holden	bcda2fae25	Don't worry about special handling for NOP.	2023-09-23 22:17:55 +01:00
Paul Holden	124889a371	RPS disassembly improvements.	2023-09-23 22:17:55 +01:00
Paul Holden	8b11f49876	Add accessors with base+offset names.	2023-09-23 22:17:55 +01:00
Paul Holden	8d70ac472b	Add a disassembler for the RSP.	2023-09-23 22:17:55 +01:00
Paul Holden	2f4c37134a	Stub out RSP.	2023-09-23 22:17:55 +01:00
Paul Holden	81e32232bb	Return whether HLE happened so we can run LLE for unhandled tasks.	2023-09-23 22:17:55 +01:00
Paul Holden	e33cf2838c	Fix out of bounds access in moveMemLight.	2023-09-23 22:17:55 +01:00
Paul Holden	798831fee9	SP PC register masking.	2023-09-23 22:17:55 +01:00
Paul Holden	ae31057a93	Remove newline.	2023-09-23 22:17:55 +01:00
Paul Holden	c35b8d531f	Fix generateCTC1Stub.	2023-09-23 22:17:55 +01:00
Paul Holden	dd996e1397	Detect underflow for D->S.	2023-09-23 22:17:55 +01:00
Paul Holden	8f4dfdd1dd	Tidy	2023-09-23 22:17:55 +01:00
Paul Holden	701d464250	Set inexact for W->S and L->S.	2023-09-23 22:17:55 +01:00
Paul Holden	09f5afa2f1	Convert function improvements.	2023-09-23 22:17:55 +01:00