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Author SHA1 Message Date
Paul Holden
0ffd40d35c cop1 half mode fixes. 2023-09-23 22:17:55 +01:00
Paul Holden
38e2d954d0 Fix cart writing with offsets. 2023-09-23 22:17:55 +01:00
Paul Holden
1be1d1ad25 Fix parity error register masking. 2023-09-23 22:17:55 +01:00
Paul Holden
1e8bbc269b Writes to fpcsr31 should be masked. 2023-09-23 22:17:55 +01:00
Paul Holden
d4bc02c0c4 FCR0 should be 0xa00. 2023-09-23 22:17:55 +01:00
Paul Holden
d567a77534 CTC1 can trigger FPE on writes. 2023-09-23 22:17:55 +01:00
Paul Holden
018ffe6595 Only the bottom 32 llAddr bits are writable. 2023-09-23 22:17:55 +01:00
Paul Holden
7076e0ac62 Explicitly handle ErrorEPC. 2023-09-23 22:17:55 +01:00
Paul Holden
8f6f2ac745 Fix writes to XContext - it's masked to upper bits and MTC0 should sign extend. 2023-09-23 22:17:55 +01:00
Paul Holden
5b6335eb72 Fix executeSetRDPOtherMode (accessing undefined vars). 2023-09-23 22:17:55 +01:00
Paul Holden
3ec1e0cfa0 Ignore writes to R0 via register accessors. 2023-09-23 22:17:55 +01:00
Paul Holden
17dee1735a setRegS32Lo is unused. 2023-09-23 22:17:55 +01:00
Paul Holden
04eb7d04d7 Use unsigned PC in dynarec code. 2023-09-23 22:17:55 +01:00
Paul Holden
5c43099064 Add debugging code to validate the dynarec pc. 2023-09-23 22:17:55 +01:00
Paul Holden
bf401ed5dd Bug fix for dynarec assembling into fragments which were previously interrupted. 2023-09-23 22:17:55 +01:00
Paul Holden
3c6ffa40dc Make sure comments end in newlines. 2023-09-23 22:17:55 +01:00
Paul Holden
640a5cfe98 Set branchDelay whether the branch is take or not. 
This fixes CAUSE_BD when an exception fires for an instruction in a delay slot when the branch isn't taken.
 2023-09-23 22:17:55 +01:00
Paul Holden
27a9668843 Make sure generated code ends in a newline. 2023-09-23 22:17:55 +01:00
Paul Holden
4a74f10da2 Automatically add newlines to generated code as needed. 2023-09-23 22:17:55 +01:00
Paul Holden
cb309f493d Reorder functions. 2023-09-23 22:17:55 +01:00
Paul Holden
6d2656282c Simplify generateGenericOpBoilerplate. 2023-09-23 22:17:55 +01:00
Paul Holden
c3ac0d676e Improve SP accuracy. 
* Fix alignment issues
* Fix wrapping within imem or dmem.
* Fix register values on dma completion
* Implement count/skip.
 2023-09-23 22:17:55 +01:00
Paul Holden
6b586231dc Emulate broken SB, SH, SD for spmem. 2023-09-23 22:17:55 +01:00
Paul Holden
27350a3465 Fix 2023-09-23 22:17:55 +01:00
Paul Holden
8512acf6b0 Fix PIF memory SH and SB. 2023-09-23 22:17:55 +01:00
Paul Holden
e1b6cd4117 Remove pif prefix. 2023-09-23 22:17:55 +01:00
Paul Holden
eed48fa5a7 Set the global bit consistently between pfne/o when setting the TLB entry. 2023-09-23 22:17:55 +01:00
Paul Holden
12b1222222 Tidy code for raising TLB and AdEl exceptions. 2023-09-23 22:17:55 +01:00
Paul Holden
352944f503 Implement entryHi as a 64 bit register. 2023-09-23 22:17:55 +01:00
Paul Holden
83d63b5ee6 vpn2mask doesn't need to be stored. 2023-09-23 22:17:55 +01:00
Paul Holden
3a848428ac Init TLBEntry fields in the constructor. 2023-09-23 22:17:55 +01:00
Paul Holden
2ae238c169 Get rid of mask2 and compute it directly. 2023-09-23 22:17:55 +01:00
Paul Holden
fcd88bd6a2 Raise a TLB Mod exception if the dirty bit is clear. 2023-09-23 22:17:55 +01:00
Paul Holden
38f3be2ce4 Perform LW load even if the result isn't stored to trigger any exceptions. 2023-09-23 22:17:55 +01:00
Paul Holden
7b2ff33ff3 Add an explicit pageMaskLowBits constant. 2023-09-23 22:17:55 +01:00
Paul Holden
3395c6102c Fix dynarec for cop1 instructions - these can raise exceptions. 2023-09-23 22:17:55 +01:00
Paul Holden
24b0bed57d Remove raiseX helpers and just use raiseException. 2023-09-23 22:17:55 +01:00
Paul Holden
d29e63dfa6 Add address helpers for dynarec. 2023-09-23 22:17:55 +01:00
Paul Holden
f6531c00f6 Expose some cop1 functions for dynarec. 2023-09-23 22:17:55 +01:00
Paul Holden
ce8ced1e4a Remove accessors for high parts of registers (unused now). 2023-09-23 22:17:55 +01:00
Paul Holden
ea29a19162 Display registers using bigints. 2023-09-23 22:17:55 +01:00
Paul Holden
2b8091e488 Add helpers to compute reg[base]+offset. 2023-09-23 22:17:55 +01:00
Paul Holden
300e985252 Move memory access helpers out to a separate module. 2023-09-23 22:17:55 +01:00
Paul Holden
e01d55c75f Always pass unsigned values to the 'slow' helpers. 2023-09-23 22:17:55 +01:00
Paul Holden
9b0e10ed09 Add 'fast' suffix to fast access routines. 
These take a signed address so it's good to make that clearer when calling them.
 2023-09-23 22:17:55 +01:00
Paul Holden
1a3f4b09cb Rename MemoryRegion functions to get/set. 
This makes them easier to distinguish from Device read/write helpers and makes it clearer they're not doing address translation.
 2023-09-23 22:17:55 +01:00
Paul Holden
12f2fbaa1b Split logging functionality out into a separate class. 2023-09-23 22:17:55 +01:00
Paul Holden
16c2a43ba4 Use the Device implementation of readU64 and write64. 2023-09-23 22:17:55 +01:00
Paul Holden
0c276c731c Provide separate functions for calculating the EA for reads and writes. 
This allows MappedMemDevice to use the default implementations of readU32 etc.
 2023-09-23 22:17:55 +01:00
Paul Holden
ba2d4a70c2 Simplify MappedMemDevice accessors. 
translateRead/Write will throw if there is a TLB exception so we don't need to check the return value.
 2023-09-23 22:17:55 +01:00