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Author	SHA1	Message	Date
Paul Holden	262a68b013	Use setVecFromAccLow for VSUBC.	2023-09-23 22:17:55 +01:00
Paul Holden	a56d52a962	Use setVecFromAccLow for VADDC.	2023-09-23 22:17:55 +01:00
Paul Holden	3a71c201c3	Update VMRG to use setVecFromAccLow.	2023-09-23 22:17:55 +01:00
Paul Holden	9e7bc6b3f3	Update logical ops to use setVecFromAccLow.	2023-09-23 22:17:55 +01:00
Paul Holden	a760ab7b7a	Set the register directly from the accumulator.	2023-09-23 22:17:55 +01:00
Paul Holden	3fdb04ddb4	Dedupe vectorSetAccFromReg.	2023-09-23 22:17:55 +01:00
Paul Holden	9d0c2e1e57	Add some helpers to reduce duplication across vector multiply instructions.	2023-09-23 22:17:55 +01:00
Paul Holden	bac7ba9f9a	Rename the main output result.	2023-09-23 22:17:55 +01:00
Paul Holden	92002d128d	Add an accessor for setting the low accumulator bits.	2023-09-23 22:17:55 +01:00
Paul Holden	024fce1c80	Fix VCO shifting. ... This is packing items into a bitfield so there's no need to account for endianness.	2023-09-23 22:17:55 +01:00
Paul Holden	6f28ab9ca3	Rename locals consistently.	2023-09-23 22:17:55 +01:00
Paul Holden	911b423571	Set the output directly from the accumulator regs in a separate pass.	2023-09-23 22:17:55 +01:00
Paul Holden	af373c34bc	Remove stray comment.	2023-09-23 22:17:55 +01:00
Paul Holden	d294761c09	Inline accum48SignExtend.	2023-09-23 22:17:55 +01:00
Paul Holden	ef6d13ca72	Add some accessors to simplfy vector multiply ops.	2023-09-23 22:17:55 +01:00
Paul Holden	7815e6193c	Get rid of newAccum temporary.	2023-09-23 22:17:55 +01:00
Paul Holden	130eebf18a	Remove TODOs: this seems to be working correctly.	2023-09-23 22:17:55 +01:00
Paul Holden	b36a070308	Emulate accumulator overflow correctly.	2023-09-23 22:17:55 +01:00
Paul Holden	f51236dee5	Implement VEXTT, VEXTQ, VEXTN, VINST, VINSQ, VINSN (all vectorZero).	2023-09-23 22:17:55 +01:00
Paul Holden	06ed51fbe5	Implement VNULL.	2023-09-23 22:17:55 +01:00
Paul Holden	ff3ed61b52	Implement VCH.	2023-09-23 22:17:55 +01:00
Paul Holden	77437a5a9b	Tidy VCL.	2023-09-23 22:17:55 +01:00
Paul Holden	f5056821c2	Implement VCL.	2023-09-23 22:17:55 +01:00
Paul Holden	d0b190b060	Add accessors for VCC hi and lo bits.	2023-09-23 22:17:55 +01:00
Paul Holden	6708988672	vuVCOReg and vuVCCReg only have one element.	2023-09-23 22:17:55 +01:00
Paul Holden	e7e7d7c771	Use u16 for VMRG.	2023-09-23 22:17:55 +01:00
Paul Holden	ec6f48741b	Implement VCR.	2023-09-23 22:17:55 +01:00
Paul Holden	b7103b2907	Implement VMRG.	2023-09-23 22:17:55 +01:00
Paul Holden	6bd8b26efb	Merge and simplify the clamp functions.	2023-09-23 22:17:55 +01:00
Paul Holden	5bd25f2c3c	Fix VMUDH.	2023-09-23 22:17:55 +01:00
Paul Holden	c1510a4c3a	Fix typo.	2023-09-23 22:17:55 +01:00
Paul Holden	9913fbb535	Disassembly for VMOV and the "VZERO" instructions.	2023-09-23 22:17:55 +01:00
Paul Holden	b32466efad	Fix element for VRCPH and VRSQH. ... n64-system test doesn't seem to test this, but this was effectively hardcoded to 0.	2023-09-23 22:17:55 +01:00
Paul Holden	e14e076348	Format	2023-09-23 22:17:55 +01:00
Paul Holden	46d5020c01	Implement more instructions which just zero the target vector.	2023-09-23 22:17:55 +01:00
Paul Holden	9085d9f061	Import rsq16.	2023-09-23 22:17:55 +01:00
Paul Holden	3013685685	Don't log the table.	2023-09-23 22:17:55 +01:00
Paul Holden	9dbdeb5e92	Implement VRSQ, VRSQL, VRSQH.	2023-09-23 22:17:55 +01:00
Paul Holden	a09c94e17d	Fix VRCPL. ... There seems to be a hardware bug around INT16_MIN.	2023-09-23 22:17:55 +01:00
Paul Holden	2b25f92378	Fix VRCP dissassembly (it's not a inverse square root).	2023-09-23 22:17:55 +01:00
Paul Holden	ae7e8bec97	Implement VRCPL and VRCPH.	2023-09-23 22:17:55 +01:00
Paul Holden	1c65424138	Improve comments for rcp16.	2023-09-23 22:17:55 +01:00
Paul Holden	49259d23b4	Implement VRCP.	2023-09-23 22:17:55 +01:00
Paul Holden	fb6fbe028a	Implement VMACQ.	2023-09-23 22:17:55 +01:00
Paul Holden	0ba80a4483	Tidy.	2023-09-23 22:17:55 +01:00
Paul Holden	7f064aa90a	Implement VRNDN.	2023-09-23 22:17:55 +01:00
Paul Holden	0a2472949c	Implement VMACF and VMACU.	2023-09-23 22:17:55 +01:00
Paul Holden	eb16f60c13	Implement VAND, VNAND, VOR, VNOR, VXOR, VNXOR, VNOP	2023-09-23 22:17:55 +01:00
Paul Holden	3f31799808	Implement VLT, VEQ, VNE, VGE.	2023-09-23 22:17:55 +01:00
Paul Holden	fd02114c71	Implement VABS.	2023-09-23 22:17:55 +01:00