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Author SHA1 Message Date
Paul Holden
f2351ce7e1 Call setBigUint64 directly from store64. 2023-09-23 22:17:55 +01:00
Paul Holden
c5518eb4a6 Remove an old/invalid FIXME. 
I think this this was fixed by throwing TLBExceptions.
 2023-09-23 22:17:55 +01:00
Paul Holden
9e381a8ac8 Implement store32masked in the Device and add a store64masked. 
This allows the exception handler to set the correct BadVAddr.
 2023-09-23 22:17:55 +01:00
Paul Holden
0e58b3261c Add some more helpers to MemoryRegion. 2023-09-23 22:17:55 +01:00
Paul Holden
f8119e7774 Implement loadU64 similarly to other functions. 2023-09-23 22:17:55 +01:00
Paul Holden
e51a3c5be5 Add some notes. 2023-09-23 22:17:55 +01:00
Paul Holden
1c7f4b78f1 Consolidate all the memory accessors in r4300.js. 2023-09-23 22:17:55 +01:00
Paul Holden
65b6876c06 Tidy presentBackBuffer. 2023-09-23 22:17:55 +01:00
Paul Holden
9228e60293 Push alignment further down memory handling callstack. 
The idea is to do this after vAddr->pAddr translation so we can report the correct BadVAddr.
 2023-09-23 22:17:55 +01:00
Paul Holden
3946907172 Implement LWL, LWR, LDL, LDR, SWL, SWL, SDL, SDR using masked writes. 
This fixes a TLB bug where TLBL is thrown rather than TLBS.
 2023-09-23 22:17:55 +01:00
Paul Holden
ea4b921941 Use gprU32 for setRegU32Extend. 2023-09-23 22:17:55 +01:00
Paul Holden
a0e5c8f09c Handle KSSEG and KSEG3 ranges. 2023-09-23 22:17:55 +01:00
Paul Holden
63a3a41e1b Handle status register similar to other control registers. 2023-09-23 22:17:55 +01:00
Paul Holden
6888fe7ee7 Fix SRAM. 2023-09-23 22:17:55 +01:00
Paul Holden
f36781a4bf Ignore the branch delay when executing a TLB exception. 
Otherwise if the delay slot triggers a TLB exceptiion we loop indefinitely.
 2023-09-23 22:17:55 +01:00
Paul Holden
b33d0956e9 Fix random reg behaviour when wired >= 32. 2023-09-23 22:17:55 +01:00
Paul Holden
1d97a3359d Improve pagemask handling. 2023-09-23 22:17:55 +01:00
Paul Holden
4872aeef9b Set XContext for TLB exceptions and clear CE bits. 2023-09-23 22:17:55 +01:00
Paul Holden
3d33d88b49 Set XContext for TLB exceptions and clear CE bits. 2023-09-23 22:17:55 +01:00
Paul Holden
0ad8d742ff Implement AdEl xcontext using 64 bits. 2023-09-23 22:17:55 +01:00
Paul Holden
86eeefc569 EPC should be sign extended. 2023-09-23 22:17:55 +01:00
Paul Holden
f7f7afe480 Fix config register masking. 2023-09-23 22:17:55 +01:00
Paul Holden
d40a65d16b Fix EntryHi mask. 2023-09-23 22:17:55 +01:00
Paul Holden
fee1794eb6 Implement DMTC0 and DMFC0 using 64 bits. 2023-09-23 22:17:55 +01:00
Paul Holden
8dfe9ffcf5 Make the control registers 64 bit. 2023-09-23 22:17:55 +01:00
Paul Holden
1c777dbad9 Rename control register members. 2023-09-23 22:17:55 +01:00
Paul Holden
46f0a3dfb6 Update some generated code to use control reg accessors. 2023-09-23 22:17:55 +01:00
Paul Holden
52b39e94f3 Tidy setTLB - no need to pass 'this' as an argument. 2023-09-23 22:17:55 +01:00
Paul Holden
74bc9b5aea Use accessor for incrementing count. 2023-09-23 22:17:55 +01:00
Paul Holden
558cd8846d Accessors for control registers. 2023-09-23 22:17:55 +01:00
Paul Holden
3a8b2e4d5f Split out a moveToControl helper and call from MTC0 and DMTC0. 2023-09-23 22:17:55 +01:00
Paul Holden
fd84dad777 Tidy 2023-09-23 22:17:55 +01:00
Paul Holden
c89f6e7490 Mask writes to EntryHi. 2023-09-23 22:17:55 +01:00
Paul Holden
727e295f02 Use nextpc+4 as the link address rather than pc+8. 
This only has an affect if an "and link" instruction is executed in a delay slot.
 2023-09-23 22:17:55 +01:00
Paul Holden
1b0af408fc Keep track of the nextPC in FragmentContext. 2023-09-23 22:17:55 +01:00
Paul Holden
12438a3cad Simplify how nextPC is set. 2023-09-23 22:17:55 +01:00
Paul Holden
38ffa3594a Ignore a local notes file I don't want to check in. 2023-09-23 22:17:55 +01:00
Paul Holden
3921b017e2 Implement cart write behaviour. 2023-09-23 22:17:55 +01:00
Paul Holden
7c4421f6df Implement broken LH/LB cart reads. 2023-09-23 22:17:55 +01:00
Paul Holden
97f8224fde Throw AdEl exception on misaligned instruction fetch. 2023-09-23 22:17:55 +01:00
Paul Holden
38bd9190ca Ensure pc is treated as a signed value so the fastpath works. 2023-09-23 22:17:55 +01:00
Paul Holden
c0d23c0965 Implement CachedMemDevice using DataView. 2023-09-23 22:17:55 +01:00
Paul Holden
f4e76c2ce2 Reimplement memory access to use dataviews. 
Benchmarks suggest DataView is now 2-2.5x faster: https://www.measurethat.net/Benchmarks/Show/26380
 2023-09-23 22:17:55 +01:00
Paul Holden
ff9e84079c Get the DataView from the MemoryRegion. 
Delete the FIXME as I'm not sure it's true any more: https://www.measurethat.net/Benchmarks/Show/26379/
 2023-09-23 22:17:55 +01:00
Paul Holden
2a35f83255 s32 buffer is only used by CachedMemDevice. 2023-09-23 22:17:55 +01:00
Paul Holden
fea6d487cf Use a DataView rather than bittwiddling. 
https://www.measurethat.net/Benchmarks/Show/26379/
 2023-09-23 22:17:55 +01:00
Paul Holden
068dfe1396 Don't format values if they're not logged. 2023-09-23 22:17:55 +01:00
Paul Holden
0bf469b568 Fix PIRamDevice readU8. 2023-09-23 22:17:55 +01:00
Paul Holden
f1ea11883d SPMem is accessible from 0xa4000000 to 0xa4040000, but wraps every 0x2000 bytes. 2023-09-23 22:17:54 +01:00
Paul Holden
79cc135707 Tidy 2023-09-23 22:17:54 +01:00