Commit graph

938 commits

Author SHA1 Message Date
Giovanni Bajo aa32804889 Fix CI Windows build
pthread.h has changed path in recent msys2 builds.
2022-03-19 15:05:28 +01:00
Adam Gashlin d386930fa2 Avoid length overflow when fetch starts beyond ROM 2022-01-24 18:41:03 +01:00
Giovanni Bajo 0902da8113 Fix SRA/SRAV opcodes
These opcodes surprisingly let the 33th bit shift in into the lower 32-bits,
before sign-extension.
2022-01-18 23:47:28 +01:00
Christopher Bonhage 9f264b3208 Emulate SRAM bank boundaries in PI read/write 2021-12-17 21:18:48 +01:00
Christopher Bonhage 6b7c2af8d4 Add support for 768Kbit SRAM save type
Fixes a Segfault when loading Dezaemon 3D.

  * Unfortunately, Dezaemon 3D does not actually work yet. It appears to
    fail the SRAM test, which still needs further investigation.

Adds an option alias for sram256k to disambiguate with new sram768k option.
2021-12-17 21:18:48 +01:00
Giovanni Bajo 87ebca00b5 Fix a few pipelining bugs with RSP
1) Setting SP_PC was not resetting the pipeline. This caused that
changing the PC within a HALT/UNHALT sequence was still causing
previous instructions in the pipeline (at the old address) to be
executed. This is not how the hardware works: SP_PC is immediate and
discards the whole pipeline.

2) BREAK did not correctly halt the processor at the right instruction,
which in turn caused resumption after HALT to execute the wrong
set of instructions. This was caused by the fact that the SP_STATUS
change was written into the EXDF latch, which in turn takes 3 cycles
to reach completion. Instead, we now use the DFWB latch, and we cause
it to abort the RSP cycle if the processor is halted. This happens
at the beginning of next cycle, which is the correct moment.

2bis) Since we are at it, use rsp_status_write to modify the RSP in
this case, rather than a direct write to the register. This change
fixes a race condition: SP_STATUS must be accessed atomically when
cen64 runs in multithreaded mode. To use rsp_status_write, we need
to introduce a nonexisting SP_SET_BROKE bit: we use the MSB, but then
mask it out in MTC0 to avoid some code to inadvertently have that bit
set.

3) When unhalting after BREAK, it's important to keep the correct
PC which comes from the EX stage (the one that was going to be
executed if BREAK didn't occur). Before, it was using the IF PC (fetch)
which is farther in the future.

Fixes #155
2021-12-17 00:23:47 +01:00
Simon Eriksson d6b5b04395 Fix arch/x86_64/rsp warnings 2021-09-07 23:11:00 +02:00
Giovanni Bajo 87ed667c38 Show Windows console when isviewer is present. 2021-09-06 23:35:40 +02:00
Christopher Bonhage 95f8dd1f02 Fix heading of os/common/local_time.c 2021-09-04 22:02:29 +02:00
Christopher Bonhage 8f64dcd8b3 Implement RTC write support
* Set local time offset when writing to Joybus or 64DD RTC.
* Refactor get_local_time to use ISO C Time APIs.

Special thanks to @jago85 and @LuigiBlood for their research!
2021-09-04 22:02:29 +02:00
Christopher Bonhage 202d2359c1 Fix buffer overflow vulnerability in pif_process
https://github.com/n64dev/cen64/issues/122
2021-07-25 20:03:58 +02:00
Simon Eriksson 6362964386
Merge pull request #203 from meeq/fix/eeprom-detection
Fix EEPROM detection Joybus status response
2021-06-26 22:33:26 +02:00
Christopher Bonhage 8c461e64c7 Improve accuracy of PIF commands
Based on EEPROM test ROM run on real hardware.
2021-06-24 07:09:06 -04:00
Christopher Bonhage 6629191f26 Resolve implicit fallthrough warnings 2021-06-24 07:09:06 -04:00
Christopher Bonhage a87c2d70f6 Fix "No EEPROM present" Joybus status response 2021-06-24 07:09:06 -04:00
Simon Eriksson 5503dd0efb
Merge pull request #189 from networkfusion/github-actions
Add Github Action workflows
2021-06-23 20:12:40 +02:00
Giovanni Bajo 8367698e20 Improve PI DMA implementation.
This is now basically perfect compared to real hardware. Verified
used the extensive testsuite here: https://github.com/rasky/n64_pi_dma_test

The only missing part is timing and making the transfer happen in
background, at least block by block.
2021-06-23 20:11:44 +02:00
Giovanni Bajo a56fa4ba41 Fix two bugs in COP0 count
First, since the internal register is kept in CPU cycles (not RCP cycles),
we need to double the value written via MTC0/DMTC0.

Second, writing a count equal to compare would cause an infinite loop
because the fault would be triggered while PC was on the instruction
doing MTC0 itself, which would be then re-executed at the end of the
exception. On real hardware, in general, when COUNT==COMPARE, the
interrupt happens a few cycles later, enough for PC to move to other
opcodes. Instead of trying to implement this, I've simply made sure
that the interrupt happened after the opcode was executed rather than
before. Also, since the internal counter is in CPU cycles, we make
sure to only raise the CAUSE bit once.
2021-06-13 23:19:07 +02:00
Giovanni Bajo 6abe0f7e55 Fix several bugs in PI DMA alignments and register reads 2021-06-07 20:36:15 +02:00
Robin Jones 42509bb74d Merge branch 'n64dev:master' into github-actions 2021-05-17 12:58:52 +01:00
Simon Eriksson eb935a85f7 rsp: Align RSP memory address in DMA to 8 2021-05-04 18:45:54 +02:00
Giovanni Bajo 622dd402f0 vr4300: fix badvaddr register in TLB exceptions.
Currently, all load/store opcodes (with the exception of LWL/LWR) mask
the lowest bit of address that causes a TLB exception in the BADVADDR
COP0 register. This is wrong because the VR4300 reports the exact
faulting address in that register, the reason being that the exception
handler must require it.
2021-05-04 00:23:24 +02:00
James Lambert 1b31ca9b3c Report full pc instead of truncated address 2021-03-12 18:20:02 +01:00
Simon Eriksson 9316569eff pi: Fix PI DMA length alignment
Fixes Yoshi's Story, F-1 World Grand Prix and probably many other games
2021-03-09 22:20:12 +01:00
James Lambert deda9f9709 Have debugger handle memory exceptions 2021-03-08 20:17:17 +01:00
Simon Eriksson 27917c7df8 rsp: Fix VNOP and VNULL 2021-03-08 20:07:19 +01:00
Simon Eriksson 89e47d2968 Add Dinosaur Planet to cart DB 2021-02-20 18:39:05 +01:00
Simon Eriksson a54cbe042f si: Fix Memory Pak initialization
Thanks to bryc for researching this issue and reviewing this fix
2021-02-20 18:11:07 +01:00
Simon Eriksson 6f9f5784bf vr4300: Fix improper handling of valid bit in TLB probe function
This fix restores GoldenEye support (#78)
2021-02-19 23:42:00 +01:00
Robin Jones 18ea3be0fb Remove un-necessary cmake change. 2021-01-22 16:09:50 +00:00
Robin Jones e05b42fb9e Check linux workflow builds. 2021-01-22 14:06:52 +00:00
Robin Jones 000b620a3a Update iconv and openal links in readme. 2021-01-22 13:57:20 +00:00
Robin Jones ac4b35b618 Cleanup toolchain file. 2021-01-22 13:36:16 +00:00
Robin Jones f95259754d Add module path 2021-01-22 13:26:27 +00:00
Robin Jones 43160673bf Add Github Action workflows 2021-01-22 12:04:57 +00:00
Tyler Stachecki 3f865dcedf
Merge pull request #187 from lambertjamesd/implement-gdb
Implement gdb
2021-01-11 17:58:54 -05:00
James Lambert 41116c3943 Document using gdb with cen64 2021-01-10 19:12:05 -07:00
James Lambert ee3d2fcc47 Implement gdb debugger 2021-01-10 17:07:29 -07:00
James Lambert 2865d107e4 Implement debugging hooks into vr4300 2021-01-10 17:07:21 -07:00
James Lambert 13720b1e29 Implement hash table 2021-01-10 17:05:35 -07:00
Tyler Stachecki b96c022e43
Merge pull request #186 from clbr/ri
Implement Reserved Instruction exception
2020-12-28 21:12:50 -05:00
Lauri Kasanen 55a46f45da Implement Reserved Instruction exception 2020-12-28 09:42:55 +02:00
Tyler Stachecki b9c36a4e7f
Merge pull request #184 from clbr/fpu
Implement fpu prid
2020-12-27 12:42:33 -05:00
Tyler Stachecki 814c272ca4
Merge pull request #159 from lambertjamesd/implement-trap-instructions
Implement trap instructions
2020-12-27 12:41:58 -05:00
James Lambert ee9cd6f0da Add correct INFO to trap macros
Correctly annotate unused parameters in trap functions
2020-12-27 10:30:26 -07:00
Lauri Kasanen 1369c191a2 Implement fpu prid 2020-12-27 09:30:20 +02:00
Tyler Stachecki ed6462e365
Merge pull request #178 from clbr/profiler
Teach the profiler about L1D misses
2020-12-26 10:44:52 -05:00
Lauri Kasanen 4316ecd0dd Implement cp0 prid 2020-12-23 16:09:12 +01:00
Lauri Kasanen 81bf10960f Teach the profiler about L1D misses 2020-12-21 19:05:07 +02:00
Lauri Kasanen 9464379f8a rsp: Remove small IO writes RMW, hw does not do that 2020-12-21 16:28:53 +01:00