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Fix two bugs in COP0 count
First, since the internal register is kept in CPU cycles (not RCP cycles), we need to double the value written via MTC0/DMTC0. Second, writing a count equal to compare would cause an infinite loop because the fault would be triggered while PC was on the instruction doing MTC0 itself, which would be then re-executed at the end of the exception. On real hardware, in general, when COUNT==COMPARE, the interrupt happens a few cycles later, enough for PC to move to other opcodes. Instead of trying to implement this, I've simply made sure that the interrupt happened after the opcode was executed rather than before. Also, since the internal counter is in CPU cycles, we make sure to only raise the CAUSE bit once.
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@ -92,6 +92,9 @@ int VR4300_DMTC0(struct vr4300 *vr4300,
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switch (dest + VR4300_REGISTER_CP0_0)
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{
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case VR4300_CP0_REGISTER_COUNT:
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rt <<= 1;
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break;
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case VR4300_CP0_REGISTER_CAUSE:
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vr4300->regs[VR4300_CP0_REGISTER_CAUSE] &= ~0x0300;
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vr4300->regs[VR4300_CP0_REGISTER_CAUSE] |= rt & 0x0300;
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@ -193,6 +196,9 @@ int VR4300_MTC0(struct vr4300 *vr4300,
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switch (dest + VR4300_REGISTER_CP0_0)
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{
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case VR4300_CP0_REGISTER_COUNT:
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rt <<= 1;
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break;
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case VR4300_CP0_REGISTER_CAUSE:
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vr4300->regs[VR4300_CP0_REGISTER_CAUSE] &= ~0x0300;
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vr4300->regs[VR4300_CP0_REGISTER_CAUSE] |= (int32_t)rt & 0x0300;
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10
vr4300/cpu.c
10
vr4300/cpu.c
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@ -30,16 +30,18 @@ void vr4300_cycle(struct vr4300 *vr4300) {
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// Increment counters.
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vr4300->regs[VR4300_CP0_REGISTER_COUNT]++;
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if ((uint32_t) (vr4300->regs[VR4300_CP0_REGISTER_COUNT] >> 1) ==
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(uint32_t) vr4300->regs[VR4300_CP0_REGISTER_COMPARE])
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vr4300->regs[VR4300_CP0_REGISTER_CAUSE] |= 0x8000;
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// We're stalling for something...
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if (pipeline->cycles_to_stall > 0)
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pipeline->cycles_to_stall--;
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else
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vr4300_cycle_(vr4300);
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if ((vr4300->regs[VR4300_CP0_REGISTER_COUNT] & 1) == 1 &&
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(uint32_t) (vr4300->regs[VR4300_CP0_REGISTER_COUNT] >> 1) ==
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(uint32_t) vr4300->regs[VR4300_CP0_REGISTER_COMPARE]) {
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vr4300->regs[VR4300_CP0_REGISTER_CAUSE] |= 0x8000;
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}
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}
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// Sets the opaque pointer used for external accesses.
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