mirror of
https://github.com/n64dev/cen64.git
synced 2024-06-22 22:12:45 -04:00
Improve PI DMA implementation.
This is now basically perfect compared to real hardware. Verified used the extensive testsuite here: https://github.com/rasky/n64_pi_dma_test The only missing part is timing and making the transfer happen in background, at least block by block.
This commit is contained in:
Giovanni Bajo
Simon Eriksson
parent
a56fa4ba41
commit
8367698e20
116
pi/controller.c
116
pi/controller.c
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@ -34,14 +34,10 @@ void pi_cycle_(struct pi_controller *pi) {
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// DMA engine is finishing up with one entry.
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if (pi->bytes_to_copy > 0) {
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uint32_t bytes = pi->bytes_to_copy;
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// XXX: Defer actual movement of bytes until... now.
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// This is a giant hack; bytes should be DMA'd slowly.
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pi->is_dma_read ? pi_dma_read(pi) : pi_dma_write(pi);
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pi->regs[PI_DRAM_ADDR_REG] = (pi->regs[PI_DRAM_ADDR_REG] + bytes + 7) & ~7;
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pi->regs[PI_CART_ADDR_REG] = (pi->regs[PI_CART_ADDR_REG] + bytes + 1) & ~1;
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pi->regs[PI_STATUS_REG] &= ~PI_STATUS_DMA_BUSY;
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pi->regs[PI_STATUS_REG] |= PI_STATUS_INTERRUPT;
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@ -79,17 +75,29 @@ static int pi_dma_read(struct pi_controller *pi) {
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else if ((source & 0x05000000) == 0x05000000)
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dd_dma_read(pi->bus->dd, source, dest, length);
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// FIXME: verify these
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pi->regs[PI_RD_LEN_REG] = 0x7F;
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pi->regs[PI_DRAM_ADDR_REG] = (pi->regs[PI_DRAM_ADDR_REG] + length + 7) & ~7;
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pi->regs[PI_CART_ADDR_REG] = (pi->regs[PI_CART_ADDR_REG] + length + 1) & ~1;
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return 0;
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}
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static void pi_rom_fetch(struct pi_controller *pi, uint32_t source, int32_t length, uint8_t *dest) {
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int l = length;
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if (source + length > pi->rom_size)
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l = pi->rom_size - source;
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memcpy(dest, pi->rom + source, l);
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// FIXME: verify this on real hardware
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memset(dest+l, 0xFF, length - l);
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}
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// Copies data from the the PI into RDRAM.
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static int pi_dma_write(struct pi_controller *pi) {
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uint32_t dest = pi->regs[PI_DRAM_ADDR_REG] & 0x7FFFFE;
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uint32_t source = pi->regs[PI_CART_ADDR_REG] & 0xFFFFFFE;
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uint32_t length = (pi->regs[PI_WR_LEN_REG] & 0xFFFFFF) + 1;
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if (dest & 0x7)
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length -= dest & 0x7;
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int32_t length = (pi->regs[PI_WR_LEN_REG] & 0xFFFFFF) + 1;
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if (pi->bus->dd->ipl_rom && (source & 0x06000000) == 0x06000000) {
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source &= 0x003FFFFF;
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@ -128,23 +136,70 @@ static int pi_dma_write(struct pi_controller *pi) {
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}
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else if (pi->rom) {
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if (source + length > pi->rom_size) {
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unsigned i;
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// PI_WR_LEN_REG has a weird behavior when read back. It almost always
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// reads as 0x7F, with the only exception of very short transfers (<= 8
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// bytes) where the actual value is affected by the DRAM alignment. This
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// is just for full accuracy, nobody is probably relying on this value.
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pi->regs[PI_WR_LEN_REG] = 0x7F;
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if (length <= 8)
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pi->regs[PI_WR_LEN_REG] -= pi->regs[PI_DRAM_ADDR_REG] & 7;
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// TODO: Check for correctness against hardware.
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// Is this the right address to use for open bus?
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for (i = (pi->regs[PI_CART_ADDR_REG] + pi->rom_size + 3) & ~0x3;
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i < pi->regs[PI_CART_ADDR_REG] + length; i += 4) {
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uint32_t word = (i >> 16) | (i & 0xFFFF0000);
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memcpy(pi->bus->ri->ram + dest, &word, sizeof(word));
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// PI DMA has an internal cache of 128 bytes ("a block"). Data is fetched
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// from ROM and then copied to RDRAM. The first block is handled "specially":
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// if the RDRAM address is not a multiple of 8, the block is shorter so
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// that the RDRAM address becomes a multiple of 8 afterwards, and a faster
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// code-path is triggered (possibly, 64-bit transfers to RDRAM).
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// This is visible because this feature is actually broken: there are two
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// bugs lingering, so that in the end Nintendo documented that only
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// 8-bytes aligned transfers were possible.
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uint8_t mem[128];
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bool first_block = true;
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while (length > 0) {
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uint32_t dest = pi->regs[PI_DRAM_ADDR_REG] & 0x7FFFFE;
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int32_t misalign = dest & 0x7;
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int32_t cur_len = length;
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int32_t block_len = 128 - misalign;
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if (cur_len > block_len)
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cur_len = block_len;
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// Decrease length (for next block). After first block, odd sizes
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// are round up.
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length -= cur_len;
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if (length & 1) length += 1;
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// Fetch block from ROM. ROM is always fetched as 16-bit words,
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// so round up the actual transfer.
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uint32_t source = pi->regs[PI_CART_ADDR_REG] & 0xFFFFFFE;
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int32_t rom_fetch_len = (cur_len + 1) & ~1;
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pi_rom_fetch(pi, source, rom_fetch_len, mem);
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pi->regs[PI_CART_ADDR_REG] += rom_fetch_len;
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// Writeback to RDRAM. Here come the lions.
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if (first_block) {
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// HARDWARE BUG #1: in the first block, there's an off-by-one, so the
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// length is actually rounded up to even size just for the last byte.
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// Notice that ROM transfers are rounded up anyway, so this additional
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// byte was already fetched from ROM.
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if (cur_len == block_len-1)
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cur_len++;
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// HARDWARE BUG #2: the length of data written back is decreased by the
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// RDRAM misalignment. This is wrong because cur_len was already
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// clamped to the block length, so this actually ends up leaving a
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// hole in RDRAM of non-transferred data at the end of the first block.
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cur_len -= misalign;
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if (cur_len < 0)
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cur_len = 0;
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}
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length = pi->rom_size - source;
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}
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memcpy(pi->bus->ri->ram+dest, mem, cur_len);
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pi->regs[PI_DRAM_ADDR_REG] += cur_len;
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pi->regs[PI_DRAM_ADDR_REG] = (pi->regs[PI_DRAM_ADDR_REG] + 7) & ~7;
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// TODO: Very hacky.
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if (source < pi->rom_size)
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memcpy(pi->bus->ri->ram + dest, pi->rom + source, length);
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first_block = false;
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}
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}
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return 0;
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@ -162,6 +217,9 @@ int pi_init(struct pi_controller *pi, struct bus_controller *bus,
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pi->flashram.data = flashram->ptr;
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pi->is_viewer = is_viewer;
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pi->regs[PI_RD_LEN_REG] = 0x7F;
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pi->regs[PI_WR_LEN_REG] = 0x7F;
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pi->bytes_to_copy = 0;
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return 0;
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}
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@ -194,15 +252,6 @@ int read_pi_regs(void *opaque, uint32_t address, uint32_t *word) {
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*word = pi->regs[reg];
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if (reg == PI_WR_LEN_REG || reg == PI_RD_LEN_REG)
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*word = 0x7F;
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else if (reg == PI_CART_ADDR_REG)
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*word &= 0xFFFFFFFE;
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else if (reg == PI_DRAM_ADDR_REG)
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*word &= 0xFFFFFE;
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debug_mmio_read(pi, pi_register_mnemonics[reg], *word);
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return 0;
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}
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@ -244,8 +293,13 @@ int write_pi_regs(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
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pi->regs[reg] &= ~dqm;
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pi->regs[reg] |= word;
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if (reg == PI_CART_ADDR_REG)
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if (reg == PI_DRAM_ADDR_REG) {
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pi->regs[reg] &= 0x00FFFFFE;
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} else if (reg == PI_CART_ADDR_REG) {
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pi->regs[reg] &= 0xFFFFFFFE;
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dd_pi_write(pi->bus->dd, word);
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}
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else if (reg == PI_WR_LEN_REG) {
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if (pi->regs[PI_DRAM_ADDR_REG] == 0xFFFFFFFF) {
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