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switch-coreboot/src/soc/intel/skylake
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Sooi, Li Cheng ac5e55604a UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 
Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC

BUG=none
BRANCH=none
TEST=none

Change-Id: Ib9887fc4f251b80b53c4ed0c0a2518b8c06eef75
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: c76e9982b2
Original-Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7
Original-Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18028
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/443928
2017-02-17 04:09:23 -08:00
..
acpi UPSTREAM: soc/intel/skylake: Add SATA interrupt for APIC mode 2017-01-19 15:14:45 -08:00
bootblock UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
include UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
nhlt UPSTREAM: soc/intel/{common,skylake}: provide common NHLT SoC support 2016-06-30 23:10:43 -07:00
romstage UPSTREAM: driver/intel/fsp1_1: Fix boot failure for non-verstage case 2017-01-19 15:14:48 -08:00
acpi.c UPSTREAM: intel/skylake: Disable FADT.8042 if NO_FADT_8042 is set 2017-02-17 04:09:16 -08:00
chip.c UPSTREAM: soc/intel/skylake: Perform CPU MP Init before FSP-S Init 2017-02-17 04:09:21 -08:00
chip.h UPSTREAM: soc/intel/common/lpss_i2c: simplify API and use common config structure 2016-11-14 19:58:28 -08:00
chip_fsp20.c UPSTREAM: soc/intel/skylake: Perform CPU MP Init before FSP-S Init 2017-02-17 04:09:21 -08:00
cpu.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
cpu_info.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
dsp.c UPSTREAM: skylake: Add Audio DSP device 2016-06-01 20:36:51 -07:00
early_smbus.c UPSTREAM: soc/intel/skylake: Define early smbus functions 2016-11-29 17:39:04 -08:00
elog.c UPSTREAM: soc/intel/skylake: Cleanup patch for Skylake SoC 2016-08-12 22:44:42 -07:00
finalize.c UPSTREAM: skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init 2016-08-19 14:19:54 -07:00
flash_controller.c UPSTREAM: soc/intel/skylake: Use the new SPI driver interface 2017-01-05 11:00:02 -08:00
gpio.c UPSTREAM: soc/intel/skylake: Remove pad configuration size hardcoding 2016-12-01 03:34:10 -08:00
i2c.c UPSTREAM: soc/intel/common/lpss_i2c: configure buses by rise/fall times 2016-11-14 19:58:56 -08:00
igd.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
irq.c UPSTREAM: soc/intel/skylake: Add FSP 2.0 support in ramstage 2016-09-22 08:54:23 -07:00
Kconfig UPSTREAM: intel/skylake: Disable FADT.8042 if NO_FADT_8042 is set 2017-02-17 04:09:16 -08:00
lpc.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
Makefile.inc UPSTREAM: soc/intel/skylake: Include I2C code in romstage 2017-01-23 02:03:25 -08:00
me.c UPSTREAM: soc/intel/skylake: Implement Global Reset MEI message 2016-10-18 22:15:03 -07:00
memmap.c UPSTREAM: soc/intel/skylake: Fix top_of_ram calculation 2016-12-01 03:34:17 -08:00
monotonic_timer.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
opregion.c UPSTREAM: skylake: Add initial FSP2.0 support 2016-09-04 19:36:45 -07:00
pch.c UPSTREAM: soc/intel/skylake: Cleanup patch for Skylake SoC 2016-08-12 22:44:42 -07:00
pcie.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
pcr.c intel/skylake: Init variable so GCC knows it's set 2016-01-15 22:41:11 +01:00
pei_data.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
pmc.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
pmutil.c UPSTREAM: soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading 2016-11-08 23:23:45 -08:00
reset.c UPSTREAM: soc/intel/skylake: Handle platform global reset 2016-10-18 22:15:06 -07:00
sata.c UPSTREAM: soc/intel/skylake: Fix SATA booting to OS issue 2016-11-08 20:29:43 -08:00
sd.c UPSTREAM: acpi: Change device properties to work as a tree 2016-07-09 01:39:55 -07:00
smbus.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
smbus_common.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
smi.c UPSTREAM: skylake: Add support for eSPI SMI events 2016-10-29 15:16:16 -07:00
smihandler.c UPSTREAM: soc/intel/skylake: Use the new SPI driver interface 2017-01-05 11:00:02 -08:00
smmrelocate.c UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
spi.c UPSTREAM: soc/intel/skylake: Use the new SPI driver interface 2017-01-05 11:00:02 -08:00
systemagent.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
tsc_freq.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
uart.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00
uart_debug.c drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
vr_config.c UPSTREAM: skylake: Add initial FSP2.0 support 2016-09-04 19:36:45 -07:00
xhci.c UPSTREAM: soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC 2017-02-17 04:09:23 -08:00