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UPSTREAM: soc/intel/skylake: Fix top_of_ram calculation

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FSP 2.0 implementation conditionally sets PMRR base based on
EnableC6Dram UPD. Therefore, handle the case of the PMRR base not being
set since FSP 2.0 changed behavior from FSP 1.1 implementation.

If prmrr base is non-zero value, then top_of_ram is prmrr base.

If Probeless trace is enabled, then deduct trace memory size from
calculated top_of_ram.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17554
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2633bf78705e36b241668a313d215d0455fba607
Reviewed-on: https://chromium-review.googlesource.com/411574
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Naresh G Solanki 2016-11-16 21:32:04 +05:30 • committed by chrome-bot
parent 5af231205c
commit 1cd6f0dbf2
1 changed files with 4 additions and 2 deletions
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6
src/soc/intel/skylake/memmap.c
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@ -150,7 +150,8 @@ u32 top_of_32bit_ram(void)
* PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before
* PRMRR_MASK MSR lock bit is set.
*/
if (smm_region_start() == 0)
top_of_ram = smm_region_start();
if (top_of_ram == 0)
return 0;
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));
@ -163,7 +164,8 @@ u32 top_of_32bit_ram(void)
* Refer to Fsp Integration Guide for the memory mapping layout.
*/
prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
top_of_ram = prmrr_base.lo;
if (prmrr_base.lo)
top_of_ram = prmrr_base.lo;
if (config->ProbelessTrace)
top_of_ram -= TRACE_MEMORY_SIZE;