mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
5f27d204bc
adaption of the v2 code, with significant cleanup and simplification. It also works in CAR mode, and has no .bss or .data usage. It provides for a way to provide AP POST codes to the BSP. Since one common file with amd changed (lapic.h) I have build-tested this against serengeti and it is fine. It builds and I'll be testing it as soon as I can find the power supply for the kontron (it got "borrowed"). Index: arch/x86/intel/core2/init_cpus.c new file. Basically an adaptation of the v2 code to v3. All global variables removed. One big change to note: there is a stack struct, and the parameters to the secondary_start are struct members. Thus the BSP can watch the AP, and, neater, the AP can POST to a shared variable and the BSP can see how far it got. Index: arch/x86/secondary.S .S startup for AP. Index: arch/x86/Kconfig Delete a dependency. Index: northbridge/intel/i945/reset_test.c Add real cold boot detection. Index: mainboard/kontron/986lcd-m/Makefile Add some new build files. Index: mainboard/kontron/986lcd-m/stage1.c Get rid of ' in #warning that confused some tool. Index: mainboard/kontron/986lcd-m/initram.c Call init_cpus. Index: mainboard/kontron/Kconfig Turn off SMM for now. Index: include/arch/x86/lapic.h Correct a static inline declaration. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1136 f3766cd6-281f-0410-b1cd-43a5c92072e9 |
||
|---|---|---|
| .. | ||
| amd/k8 | ||
| arch | ||
| amd_geodelx.h | ||
| byteorder.h | ||
| cpu.h | ||
| div64.h | ||
| io.h | ||
| lapic.h | ||
| lapic_def.h | ||
| legacy.h | ||
| macros.h | ||
| msr.h | ||
| mtrr.h | ||
| multiboot.h | ||
| pci_ops.h | ||
| pirq_routing.h | ||
| qemu.h | ||
| smm.h | ||
| stage1.h | ||
| swab.h | ||
| types.h | ||
| via_c7.h | ||