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https://github.com/fail0verflow/switch-coreboot.git
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b6c89edb04
2 size calculations. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
#ifndef ARCH_X86_MTRR_H
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#define ARCH_X86_MTRR_H
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/* These are the region types */
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#define MTRR_TYPE_UNCACHEABLE 0
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#define MTRR_TYPE_WRCOMB 1
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/*#define MTRR_TYPE_ 2*/
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/*#define MTRR_TYPE_ 3*/
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#define MTRR_TYPE_WRTHROUGH 4
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#define MTRR_TYPE_WRPROT 5
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#define MTRR_TYPE_WRBACK 6
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#define MTRR_NUM_TYPES 7
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#define MTRRcap_MSR 0x0fe
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#define MTRRdefType_MSR 0x2ff
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#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
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#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define NUM_FIXED_RANGES 88
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#define MTRRfix64K_00000_MSR 0x250
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#define MTRRfix16K_80000_MSR 0x258
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#define MTRRfix16K_A0000_MSR 0x259
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#define MTRRfix4K_C0000_MSR 0x268
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#define MTRRfix4K_C8000_MSR 0x269
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#define MTRRfix4K_D0000_MSR 0x26a
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#define MTRRfix4K_D8000_MSR 0x26b
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#define MTRRfix4K_E0000_MSR 0x26c
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#define MTRRfix4K_E8000_MSR 0x26d
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#define MTRRfix4K_F0000_MSR 0x26e
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#define MTRRfix4K_F8000_MSR 0x26f
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#if !defined (ASSEMBLY)
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void x86_setup_var_mtrrs(unsigned address_bits);
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void x86_setup_mtrrs(unsigned address_bits);
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int x86_mtrr_check(void);
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void stage1_set_fix_mtrr(u32 reg, u8 type);
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u8 stage1_range_to_mtrr(u8 reg, u32 range_startk, u32 range_sizek,
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u8 type, u32 address_bits);
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u32 stage1_resk(u64 value);
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#endif
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#endif /* ARCH_X86_MTRR_H */
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