The write protect is active high, not active low. Fix. After fixing I
can see this after removing the screw:
$ crossystem | grep wpsw_boot
wpsw_boot = 0
Putting the screw in shows:
$ crossystem | grep wpsw_boot
wpsw_boot = 1
Caution: this CL contains explicit material. It explicitly sets the
pullup on the WP GPIO even though that's the boot default.
BRANCH=None
BUG=chrome-os-partner:55933
TEST=See desc.
Change-Id: Ie65db9cf182b0a0a05ae412f86904df6b239e0f4
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366131
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add a Kconfig value to enable the console during postcar. Add a call
to console_init at the beginning of the postcar stage in exit_car.S.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Change-Id: I36982430d0619e1ae8a3745964e497e9c11cf3db
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16001
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/366300
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Display the MTRRs after they have been updated during the postcar stage.
TEST=Build and run on Galileo Gen2
BUG=None
BRANCH=None
Change-Id: Iaefedb737ee601c318fc0b6071943182cc7c11d7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15991
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366299
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Newer Linux kernels fail to detect the initramfs using the old 16M
offset. Increase the offset to the minimum working value, 64M.
Tested-on: qemu pc, 64-bit virtual CPU, linux 4.6 x86_64
BUG=None
BRANCH=None
TEST=None
Change-Id: Ib124c1e1fdb4e43dfb74e19d6126b575fd706325
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/15999
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/366298
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch adds two SPD files with different DDR3 clk settings.
The user can choose which setting to use.
Lower clk settings saves power under load.
SoC Model GX-411GA supports only up to DDR3-1066 clk mode.
Both SPD settings were tested with memtest for several hours.
Power saving is around half a watt under heavy memory load.
Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0
BUG=None
BRANCH=None
TEST=None
Change-Id: I2fb09a7f83e32019f78634a68850c37229692068
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15907
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/366291
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This adds support for Nuvoton NCT6791D Super I/O chips.
Makes use of the common Nuvoton early_serial.c.
Based on the Datasheet supplied by Nuvoton.
Datasheet Version: January 8th, 2016 Revision 1.11
BUG=None
BRANCH=None
TEST=None
Change-Id: Id7f44c0f2a683bd7f91472ef09bdd6f2240f3569
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15967
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/366289
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This probably never happens, but since we already test for the presence
of the device, it makes no sense to try to configure it after its
absense was determined.
BUG=None
BRANCH=None
TEST=None
Change-Id: Id5d321c712af70c374307643ced5c995431d324f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347362
Reviewed-on: https://review.coreboot.org/15982
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/366283
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn
returns an int (with -1 for "error"), so use int for devfn.
BUG=None
BRANCH=None
TEST=None
Change-Id: Icec29cdb2afab4a69c04660fef32557c4de4c5d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1357450, #1357449
Reviewed-on: https://review.coreboot.org/15964
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/366274
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch enables DPTF support for Intel Amenia
platform, adds the ASL settings specific to Amenia
boards.
BUG=chrome-os-partner:53096
BRANCH=None
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Amenia board. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I2a23eea3678c13b04f714a74ff8055391dac2071
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15094
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366272
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch enables DPTF support for Google Reef
platform, adds the ASL settings specific to Reef
boards.
BUG=chrome-os-partner:53096
BRANCH=None
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Reef boards. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I4c67980925178f509c8aed9722946d2d10a23911
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15640
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366271
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Run the command below to format the files `irq_tables.c` of (mostly AMD)
mainboards correctly with GNU indent 2.2.10.
```
$ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l
```
Fix up the following two checkpatch.pl errors manually.
```
ERROR: that open brace { should be on the previous line
+ uint8_t reg[8] =
+ { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 };
ERROR: that open brace { should be on the previous line
+ uint8_t irq[8] =
+ { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 };
```
This is needed, so that follow-up commits, fixing checkpatch.pl errors
and warnings, wont run into conflicts with the git commit hooks, when
for example, spaces instead of tabs are used for indentation.
BUG=None
BRANCH=None
TEST=None
Change-Id: I3a13994570b18de5753f95d6dcfcd2cf523fd321
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/15932
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/366269
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This adds support for the Nuvoton NCT6791D Super I/O chip to the
superiotool.
The implementation is based on the Datasheet supplied by Nuvoton:
Datasheet Version: January 8th, 2016 Revision 1.11
Datasheet deviation:
- Defaults for control registers 0x20 and 0x21 are invalid.
Datasheet: 0xc562. Actual: 0xc803.
BUG=None
BRANCH=None
TEST=None
Change-Id: Iac3027ee924e0b4029bb7eb3200a2a7c0b6ca1b2
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15252
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/366268
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Almost all of the places where we have the degree symbol '', it's
encoded as 0xc2 0xb0 (utf-8 encoding). There are a few places where it
is encoded as just a high ascii byte: 0xb0. Editors that support the
high ascii 0xb0 seem to support the utf-8 0xc2 0xb0 encoding as well,
but the opposite does not seem to be true.
Change the high-ascii degree symbols to utf-8 encoding.
BUG=None
BRANCH=None
TEST=None
Change-Id: I4b2fc603d57ab140c6bd6a9e8fe3eaa480d39d68
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15978
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/366219
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This removes the newlines from all files found by the new
int-015-final-newlines script.
BUG=None
BRANCH=None
TEST=None
Change-Id: I89fcb55ff285e4793d7f057f684187359334cb70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/366218
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Turned out that there are versions of the patch command that use the
left hand side path for new files created by a patch. This behavior is
incompatible with some of our patches. Stripping the topmost dir from
the path with -p1 helps.
While touching that line, I couldn't resist to drop a command
substituion (the `echo $patch`). It really shouldn't be necessary as the
path to the patch file is already expanded in the head of the for loop.
BUG=None
BRANCH=None
TEST=None
Change-Id: I090caacc0e3eed4bd993717368a7f0afc0622bb1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/15908
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/366217
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Keep this enabled by default as most x86 platforms could have PCI-e
slots equipped with one of these Intel WiFi adapters.
The Kconfig entries under google boards had no function previously,
the variable was never referenced.
BUG=None
BRANCH=None
TEST=None
Change-Id: I0dce909b07067eb4f23c89cddff32a004fdc52f0
Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15931
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366216
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add next generation of BAPs (https://www.unibap.com/) SOC module,
called ode_e21XX.
Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini),
but it includes a new AMD G-Series GX-412HC (Steppe Eagle)
and an updated Microsemi FPGA.
Changes to Olivehillplus:
- Add SuperIO Fintek F81866D
- Soldered down DDR3 with ECC
- User can choose between different DDR3 clk settings
(lowest setting can save up to 1.2W)
- Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3
Tested with:
- Payload SeaBIOS 1.9.1
- Lubuntu 16.04, Kernel 4.4.0
- Windows 10 (UART functionality)
Known problems:
- S3 not working
- IOMMU not working
BUG=None
BRANCH=None
TEST=None
Change-Id: Iefe436a2b7631e3ea9380838dbc216810a2f03ee
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15918
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/366213
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
