Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.
Source: Intel Baytrail/ValleyView UEFI reference code
BUG=none
BRANCH=none
TEST=none
Change-Id: I69c3bd55f6340770402a67af2601e5df965b2b60
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 930577ac7b
Original-Change-Id: Icc9b27aaa14583d11d325e43d9165ddda72ca865
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20080
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531199
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.
Source: Intel Braswell UEFI reference code
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic4cffd5dce2387288f5b8559f497230b22ddce90
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f6cfa71217
Original-Change-Id: I1d97b5a07bf732c27caf57904c138b120b93ca81
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20079
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531198
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use common init_igd_opregion method.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7b93ffe4853c129e3acc0126fb85fe8519d058ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9095e2f50e
Original-Change-Id: Ie70a49fd532b7ad7679dc558cc4a019a273a0602
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19906
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531197
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Copy Haswell's init_igd_opregion to common folder.
Remove platform specific code.
Will replace all Intel NB implementations.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3886dfb0c4a3c98cfb6c0c68a14852d88f0f5a8d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 96c3ef81fc
Original-Change-Id: I14dfb5986df264ffd71183a159f98b79e8e3230e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19905
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531196
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD
specifications.
BUG=none
BRANCH=none
TEST=none
Change-Id: I35c9634f36868caf03438e688c1ec5ab484c2449
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 87f7588c50
Original-Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20058
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/531195
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for intel/strago
and google/cyan as to not break compilation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I39d845ba3b6d07d8bb5f63f663316750f03f20a6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a67ffb6ea
Original-Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20055
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibca733ea7c557899ff2f8d86362cccd7a41bbcca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 397c7b3411
Original-Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19976
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9f566b4c7117981e58709d3b8b52b410a5e3bbaf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dc1b78130a
Original-Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19975
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c179884707380e1417a251db8f70d0a915572af
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b9959e279c
Original-Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20044
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531190
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update user facing camera i2c address to 0x36.
BUG=None
TEST=Build & boot on soraka. Make sure user facing camera is detected.
Change-Id: Id441041035e8a2962c859cac93d02858fc84d625
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5e10422df2
Original-Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20023
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The RTC RX6110SA has several configuration options which might be
interesting to set. To make this setup independent of the driver itself
but let it still be configurable on mainboard level, add more
configuration options to the chip driver.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2050f013241e3ff6021ec1eb9aabf91f6d725229
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0dc405de98
Original-Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20084
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/531187
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5f46992e4d536a21922721eb97061a78e067e74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6ab7e5e090
Original-Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19995
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/528271
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add additional ACPI opcodes, that are going to be used in the
following commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icc2d79902965feca18c5c502dffcd189329b4c44
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a038835716
Original-Change-Id: I20c3aa5a1412e5ef68831027137e9ed9e26ddbc9
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20087
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/528270
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix regression introduced by commit 5c026445
(drivers/intel/wifi: Add support for generating SSDT table)
In case the regular PCI path is taken, there're no chip_ops and the code
will segfault. The bug was covered by other bugs that caused this code
to never execute.
Add NULL pointer checks and only fill in device name if one is provided.
Tested on Lenovo T430 and wifi card 8086:0085.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieb95c7f281d8f69ecf3cc2e0e176a24923891a2f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6086b4ee38
Original-Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/20082
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528269
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove spi_init definitions which:
1. Do nothing
2. Set static global variables to 0
BUG=none
BRANCH=none
TEST=none
Change-Id: I471dc31bf496936968c3a4a55f7ecac517752e5d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2dafd89769
Original-Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20039
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/528265
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add support for ELAN 5515 device.
BUG=b:62331218
Change-Id: I1be493f7fbce0a31fefdc589c063d1561a384c5e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5677e7da4b
Original-Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20040
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528264
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
These Kconfig files had help text that was not indented further than
the 'help' keyword.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia652cab86f965ba95ad2105f37493c7a53c52f97
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f482396625
Original-Change-Id: Ia9fdb22c0f5f0cec0c9d08aa6603b4ce8d60d9a3
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19850
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528263
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch fixes ACPI debug print issue reported internally
while using APRT asl method. Potentially some junk characters
gets added into final print buffer due to LPSS MMIO register
space is 32 bit width and ADBG is one byte at a time.
TEST=Built and boo eve to ensure to be able to get ASL console
log without any corruption.
Change-Id: Ia5a03c7874d5b50f6259a95c8e8896d0e616cfd7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f0c7be4e63
Original-Change-Id: I0b6af789c0ffc79f7fee4652b4aa6a125b182296
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20009
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528261
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
BUG=none
BRANCH=none
TEST=none
Change-Id: I280a7abeada01b4d158b2d65c3b59f1b98b81ad9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e18e6427d0
Original-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20029
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528259
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
BUG=none
BRANCH=none
TEST=none
Change-Id: I881e55138a6114c67585ce37d4d719fe2626b83a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a8843dee58
Original-Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20034
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528256
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Wrapping the long line tries to address a warning by `checkpatch.pl`,
but the line is still over 80 characters long.
BUG=none
BRANCH=none
TEST=none
Change-Id: If63c7ff3fb041b070dc815ffe05592edbb03dbec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 619e83045a
Original-Change-Id: Ib75d4da1880624eb83f7a419cb6762f1c4c2a7b2
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20033
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528255
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The comma-separated PCI vendor and device ID is used to associate the
VGA BIOS to the video device by using it as the file name of the VGA
Option ROM.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ideb80c381f491925dba2931448fe125a3f54e8f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e213bf3767
Original-Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18741
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528254
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove PCI IDs inclusion from soc header rather referring those
from device/pci_ids.h.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie89777bc73c7061676e740f10ada60e1391b312d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c2165671b0
Original-Change-Id: I490da3e336fb6f8194d5fba800132f550ed5ab37
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20015
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Changes the offsets of some options so that options that span multiple
bytes are byte aligned.
To make the cmos.layout file more consistent some things where moved
around in the cmos.layout of thinkpads X200 and T400.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8736136043c526817fc12f52d37a5a1db4fb95b9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 00b9f4c4b1
Original-Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18321
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/528188
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Place `tdp_pl2_override` above the FSP options as it's not an FSP option.
BUG=none
BRANCH=none
TEST=none
Change-Id: I01bda06d9ef57890891757ed94baf2e5bb4e2f8f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4a47e4b8ee
Original-Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19637
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528184
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Provide some enums instead of unreadable comments that are usually
copied all over.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3286388b00ec6800f7a5b6a5c133d96e7d7e8162
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 503965f939
Original-Change-Id: Iff551565647f28ecb226e1df633b4deec0ab0a7f
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19636
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528183
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
FSP_IMAGE_ID and FSP_IMAGE_REV are defined in `FspUpdVpd.h`. Check
against these to avoid mismatching definitions in coreboot and the
FSP blob.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0b936414f7c4d0c17800ea59c2bb3665cf700f6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e7947df462
Original-Change-Id: Ic86229e7f0c2d0525b8a79add292c6c81a349aa6
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19635
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528182
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A new variant copied from reef.
Allow override of the SKU.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5ad68505988d7c79d64b8654b3810669a4e7940
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b09933a2eb
Original-Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/20020
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/524606
This typo existed in code before rewriting for using
defines and it's clearly visible after rewrite.
Previously it was writing to reserved area of GMBUS0 register,
while values are matching those of GMBUS1.
This line probably is a no-op since it's just sending the STOP
again (without an address set this time).
BUG=none
BRANCH=none
TEST=none
Change-Id: I7bcbaff545f45f0bcb6c23d7f4496f10681ef2eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34e10871f9
Original-Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e
Original-Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/16341
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/524605
set_var_mtrr() and get_free_var_mtrr() don't need to be guarded
against various stages. It just complicates code which lives
in a compilation unit that is compiled for multiple stages by
needing to reflect the same guarding. Instead, just drop the
declaration guard. earlymtrr.c is still just compiled for earlier
stages, but if needed it's easy to move to a mtrr_util.c that
is compiled for all stages.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2e78ef748b721b2a7ed08250ed0ffcda4dbffa08
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d86e0e6638
Original-Change-Id: Id6be6f613771380d5ce803eacf1a0c8b230790b6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20018
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/524598
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each rambi variant has a different USB port config.
Port data currently available for only candy and squawks;
other variants to be added once data obtained.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5db0b81369ab60dbef8e59bfddd846bbd494950
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74e1fb0b1a
Original-Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19974
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524597
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each jecht variant has a different USB port config.
BUG=none
BRANCH=none
TEST=none
Change-Id: I10e318e7bb6ea6ee3f4b0d5c210c4c7d639adce4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f069edb975
Original-Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19971
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524596
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each auron variant has a different USB port config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic677f49c4355da471c50b55afc2a6351d8e0f27d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c3c7a1dcb
Original-Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19970
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524595
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I686dcc6b630a89d37e80276e9534923e8e6aad87
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b79d058767
Original-Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19969
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/524594
Include <arch/io.h> since functions use types defined in there.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icbfc9f69054b75bd94397da27ebff55b86378190
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f7ca225a7e
Original-Change-Id: Iba6bcea4377359c15e3148062458186ee222b8e2
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20004
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/524592
If CONSOLE_SPI_FLASH config is enabled, we write the cbmem
messages to the 'CONSOLE' area in FMAP which allows us to grab the
log when we read the flash.
This is useful when you don't have usb debugging, and
UART lines are hard to find. Since a failure to boot would
require a hardware flasher anyways, we can get the log
at the same time.
This feature should only be used when no alternative is
found and only when we can't boot the system, because
excessive writes to the flash is not recommended.
This has been tested on purism/librem13 v2 and librem 15 v3 which
run Intel Skylake hardware. It has not been tested on other archs
or with a driver other than the fast_spi.
BUG=none
BRANCH=none
TEST=none
Change-Id: I775e9fdbae152d57d659d300644a548bc5daed02
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c4b4ff3b1f
Original-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19849
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/523981
Since dual-channel setups use same RAM/SPD for both channels,
populate spd_data[1] with same SPD data as spd_data[0],
allowing info for both channels to propogate into the
SBMIOS tables.
Clean up calculations using SPD length to avoid repetition.
Changes modeled after google/auron variants.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4f74548fd00577e1730c4535b8ea5c59b096f3ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cadd7c7ed3
Original-Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19981
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/523980
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed
TEST: boot Windows on google/butterfly, observe battery data
reported correctly.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4b79699fd993574addaf1a8cc0dfdb43e1f575b5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: af4c0a431c
Original-Change-Id: I395cc7fbdf26c8cc816e47107e552c0533580fa1
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19961
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523979
sata_devslp_disable was set to work around some buggy SSD
firmware, but as it's disabled by default in both Linux and
Windows, no reason to disable at the firmware level when
many properly-functioning SSDs can take advantage of power
savings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f317e963dbc88a766be5da9e2266e328c4ed1ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a5c6201da
Original-Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19957
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523977
Fix for all Sandy-Bridge and Ivy-Bridge devices.
Remove unused option "hyper_threading".
Increase CMOS checksum range to cover all user adjustable settings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3d0eab9eb780aff5e132a96fe436cae212426c69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3de6d38642
Original-Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19955
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/523976
This is to align with the SD_CD GpioInt setting in acpi
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: Id2c151cb8549e0c447c4a1494556f1cf6a55d0ac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8cb70914ca
Original-Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20001
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523975
Currently, there is no macro to set GPIO interrupt trigger mode.
The purpose is to make coreboot set same trigger mode as GpioInt
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: I3c9b8ac398708d6bde8a41044a77fed8acc8daed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4db78e39da
Original-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19992
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523974
