Only board using this code was tyan s2735 which was removed in
f76de841f1 "[REMOVAL] tyan/s2735"
BUG=none
BRANCH=none
TEST=none
Change-Id: I75d2a72adf24ed89d74631f4101ab8b74c26f198
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bd23bd62b4
Original-Change-Id: I03a101adc1eedfa9669e0b44c54c2c6fa08bd5f2
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19507
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/509527
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=b:37712455
Change-Id: Ia5aa6665db0f8199de8d2cf363272d7e2b676363
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 365d97e938
Original-Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19766
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509526
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix SPD as per the vendor-provided data.
BUG=b:37712790
Change-Id: Id2054c54ec61c7bd3e9161c70506f45d31fd36d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 77be7339cd
Original-Change-Id: Ib87c316479f4a05e64ca4acb540d7aacfa7338e9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19749
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509525
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Define a new spi_flash_ops structure, move all spi flash operations to
this structure and add a pointer to this structure in struct spi_flash.
BUG=b:38330715
Change-Id: I29deaa94b0339972aa016b77a80344da6abadd06
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e2fc5e25f2
Original-Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19757
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509524
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it
so that drivers can use it outside spi_flash.c.
2. Make southbridge intel spi driver use spi_flash_generic_probe if
spi_is_multichip returns 0.
3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to
provide specialized probe functions. With this change, the specialized
spi flash probe functions are now associated with a particular spi
ctrlr structure and no longer disconnected from the spi controller.
BUG=b:38330715
Change-Id: I996ff78f75296cc5bc38b6e760545b9b7dd810c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a1491574ef
Original-Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19708
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509523
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Pointer to spi_slave structure can be passed in as const to spi flash
probe functions since the probe functions do not need to modify the
slave properties.
BUG=b:38330715
Change-Id: I817a51fc7b480f6532941fccd08a6179dbc14378
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bd9e32efdd
Original-Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19707
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509522
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove unused function declaration spi_fram_probe_ramtron.
BUG=b:38330715
Change-Id: I05900361e86178b297c29f57d7e907a237cf3452
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7863395ad1
Original-Change-Id: I05e6c5c2b97d6c8a726c0e443ad855f9bcb703f9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19706
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509521
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: Iea541abe70577dc357e8de4f62b5cd4b75c889e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 30221b45e0
Original-Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19705
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509520
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add a new member page_size to spi_flash structure so that the various
spi flash drivers can store this info in spi_flash along with the
other sizes (sector size and total size) during flash probe. This
removes the need to have {driver}_spi_flash structure in every spi
flash driver.
This is part of patch series to clean up the SPI flash and SPI driver
interface.
BUG=b:38330715
Change-Id: I1643c17f10226e943a3f94d4619f7e87f4b6777c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fc1a123aa7
Original-Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19704
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509519
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of storing spi flash device structure in spi flash driver, use
boot_device_spi_flash callback to obtain pointer to boot device spi
flash structure.
BUG=b:38330715
Change-Id: I83a384ce1b417869167d9dbeb38ed7a9900f0e11
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f422fd2c78
Original-Change-Id: Idd50b7644d1a4be8b62d38cc9239feae2215103c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19703
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509518
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This allows callers to retrieve handle to the boot device spi_flash structure.
BUG=b:38330715
Change-Id: Ica5e952ccca4f73dc35bfba31e4f9e0d880f0390
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 78bc6ddfd0
Original-Change-Id: I1c07327115e0449cbd84d163218da76a6fa2cea0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19726
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/509517
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested and working:
* HDD LED
* Booting GNU Linux 4.9 from HDD using SeaBios
* Booting GNU Linux 4.9 from USB using SeaBios
* Native GFX init
* All Fn function keys
* Speakers
* PCIe Wifi
* Camera
* WWAN
* Fan (Dynamic Thermal Managment)
* Flashing using internal programmer
* Dual memory DIMMs running at up to DDR3-1866
* AC events
* Touchpad, trackball and keyboard
* USB3 ports running at SuperSpeed
* Ethernet
* Headphone jack
* Speaker mute
* Microphone mute
* Volume keys
* Fingerprint sensor
* Lid switch
* Thinklight
* TPM (disable SeaBios CONFIG_TCGBIOS)
* CMOS options:
** power_on_after_fail
** reboot_counter
** boot_option
** gfx_uma_size
** usb_always_on
Untested:
* Booting Windows
* Hybrid graphics
* Docking station
* VGA
Broken:
* Wifi LED is always on
BUG=none
BRANCH=none
TEST=none
Change-Id: I8e9aa289a838691ce6edcddeb42cb4d1a865a609
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 714baa119b
Original-Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18011
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/509516
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Id27b75d20f71bdb6c532796944e62aea79d9174d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aeae34ffa4
Original-Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19551
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/509515
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Hide device 4 and device 7 if disabled.
Allows devicetree settings to take effect.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4f94c1f37cc85c293e2e5d8f41545d67ae11a9de
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ecd4be8114
Original-Change-Id: I64a19e2bbdb1640e1d732f6e4486f73cbb0bda81
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19689
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/509514
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The 'cbmem -1' flag that cuts off console output before the last boot
will ignore content from earlier stages if it was truncated due to lack
of pre-CBMEM console space. This patch makes the "log truncated" message
more specific and adds it as an additional cut-off marker to 'cbmem -1'
to counteract that problem.
Also raise the log level of the coreboot banner one step to BIOS_NOTICE
to make it more likely to be included in the output for 'cbmem -1' to
find. (I believe NOTICE is reasonable but I wouldn't want to go as far
as WARN which should be reserved for actual problems. Of course this is
not ideal, but then again, our whole log-level system really isn't... it
would be better if we could make it always print a banner to the CBMEM
console without affecting the UART at the same time, but that would
require a larger amount of work.)
BUG=none
BRANCH=none
TEST=none
Change-Id: I71f5ae9e44509608d3c47edcb4a7c869d0d650db
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d906bb68c3
Original-Change-Id: I58288593dfa757e14f4a9da4ffa7e27b0b66feb9
Original-Reported-by: https://ticket.coreboot.org/issues/117
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19720
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509513
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This reverts commit 6434755b96.
Revert the revert to get the touchpad ID ready for
the new touchpad firmware again.
BUG=b:35581264
BRANCH=none
TEST=none
Change-Id: I0c70f2c7c844d9199b9098783c24a6a0460263cc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506785
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
We have several different UART implementations of which three support a
timeout when receiving characters. In all of these three implementations
there is a bug where when the timeout is hit the last received character
will be returned instead of the needed 0.
The problem is that the timeout variable i is decremented after it has
been checked in the while-loop. That leads to the fact that when the
while-loop is aborted due to a timeout i will contain 0xffffffff and not
0. Thus in turn will fool the following if-statement leading to wrong
return value to the caller in this case. Therefore the caller will see a
received character event if there is none.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b846abcdbc3b0e4777ff541dbb0ae7aa9f5f8d5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 43314ffae5
Original-Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19731
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508780
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6ab4e00cbae38bbbc6f8633a3d77944a25a6ecdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e87564ffe7
Original-Change-Id: I0c375e5da0dfef6cef0c50272356cd32a87b1ff6
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19346
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508779
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie72f645e841d758ad4a275c39111c3a785ddd883
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 61be3603f4
Original-Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19328
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/508778
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
AGESA and binaryPI boards have no easy way to determine correct
cbmem_top() location early enough when GFXUMA is enabled, so they
will use these functions with EARLY_CBMEM_INIT as well.
At the end of AmdInitPost() the decisions of UMA base and size
have not been written to hardware yet. The decisions are stored
inside AGESA heap object we cannot locate from coreboot proper
until after AmdInitEnv().
Modify code such that weak backup functions are only defined
for LATE_CBMEM_INIT; they are somewhat troublesome to handle.
BUG=none
BRANCH=none
TEST=none
Change-Id: I507ef40b77f20c76b3178654c397a4130092240d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a7dd645594
Original-Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19306
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/508776
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
In the intel/common/block
* Move I2C common code from intel/common to intel/common/block.
* Split the code into common, early init and post mem init stages and put it
in lpss_i2c.c, i2c_early.c and i2c.c respectively.
* Declare functions for getting platform specific i2c bus config and
mapping bus to devfn and vice versa, that have to be implemented by SoC.
In skylake/apollolake
* Stop using code from soc/intel/common/lpss_i2c.c.
* Remove early i2c initialization code from bootblock.
* Refactor i2c.c file to implement SoC specific methods
required by the I2C IP block.
BUG=none
BRANCH=none
TEST=none
Change-Id: I82264b8a57b3cfd8be2281b7f3f32da158d0ac32
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ae6a4b6d3c
Original-Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19468
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508775
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
TEST=Boot from scarlet, and mipi panel works
Change-Id: I28ae05e1d3681a6012da80cf2e2dae196110559c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 36b09b8a6c
Original-Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19700
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508774
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch configures clock for mipi and then
adds mipi driver for support innolux-p079zca
mipi panel in rk3399 scarlet.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7e18b13b1403cb731aa8b5bd214bd35fd5f96637
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fe122d4dfc
Original-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19477
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508773
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The hang was caused by deasserting the reset before, it had been delayed 20us
fixing the hang issue.
So we can remove this delay for now.
BUG=none
BRANCH=none
TEST=none
Change-Id: I12d09cd0d25974bbaffaf444f2af4697d85c2648
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2684efc492
Original-Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19699
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508772
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Program eMMC DLL settings for mc_apl1 mainboard, after that system can
boot up with eMMC successfully.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ife34e1b5079eca8e51f2270439dbe05d613ed688
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c7ccb6b29f
Original-Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19712
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/508771
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The mainboard siemens/mc_apl1 uses an external I/O port for console
output. For this reason we need to activate the 8250 LPC UART.
BUG=none
BRANCH=none
TEST=none
Change-Id: I32e68e06a64308bf56010ce2e8e48ba42fd788b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ae10ec6239
Original-Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19694
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508770
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If there is an external 8250 UART, one needs to enable the appropriate
address ranges before console_init() is called so that the init sequence
can reach the external UART.
Furthermore FSPM needs different settings for an external UART port. For
this, the function fill_console_params() has to be adapted.
BUG=none
BRANCH=none
TEST=none
Change-Id: I13710c1e25d628430b3c7d7b015eebb81046ef65
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9e9cf270c4
Original-Change-Id: I62c7d0b54edd18acf793849aef352afbcaeb68b9
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19693
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508769
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This device is no longer directly connected to the SOC so it
does not need to be enabled in coreboot.
BUG=b:35648259
TEST=build and boot on Eve
Change-Id: I5c13d993a2f37a023208fba2b745b70e9db9e310
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: c5eab98e78
Original-Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19728
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/507638
The touchpad frequency was still slightly above 400kHz so tweak
the timing values manually to get under the spec limit.
BUG=b:35583133
TEST=verified the bus frequency with a scope to be < 400kHz
Change-Id: I07b171ebe912bf603049656e48beeeabdd56fef6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 4f7d536ed3
Original-Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19727
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/507637
disable_turbo function can be used to disable turbo mode
on each processor by settings MSR 0x1A0 bit 38.
This option will help to perform some quick test
without enabling turbo mode.
BUG=none
BRANCH=none
TEST=none
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 7bde848d62
Original-Change-Id: If3e387e16e9fa6f63cb0ffff6ab2759b447e7c5c
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19674
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id35173ff75e9ae098ace61dd2c6cea38026213e1
Reviewed-on: https://chromium-review.googlesource.com/506902
- Put parameter comments and help text in the same order as the actual
parameters.
- Don't clone a new release tree from coreboot.org if a tree already
exists.
- Change COMMIT_ID parameter from optional to required. If it was
omitted previously, the head of the master branch would be used.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5c5a764e9f2fac4737c70f0c455050521a47da26
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7a00a63829
Original-Change-Id: Ifa434a4911dec777004788e3cf4e3436875d929b
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19126
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/506201
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
They do 64bit accesses, and gcc does the necessary fix ups to handle
32bit values as zero-padded 64bit values.
clang, however, isn't happy with it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6d3b9f81d572d980f3a4fdd090819bf23812ce4a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ff2938ff4b
Original-Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/19661
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506200
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The former only exists with a custom patch while the latter is supported
by clang and in the absense of libgcc even points to clang's own runtime
libraries.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibac78ca45bd0a4376e72eb15638a47efca32613e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6d3ce3a996
Original-Change-Id: I1e30d5518cf78e1d66925d6f2ccada60a43bb4f8
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/19658
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec@google.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/506199
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I7488d471b8e4c4a5fb8ea79302a1b39eee1e3333
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bddf86a259
Original-Change-Id: I5fcc83328441ccfb34ee63a7406d26e393633c21
Original-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19685
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/506198
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
There is code to adjust the mapping down if a mmap fails
at a physical address. However, if the address is less
than the page size of the system then the physical offset will
underflow. This can actually cause a kernel panic on when
operating on /dev/mem.
The failing condition happens when the requested mapping at 0
fails in the kernel. The fallback path is taken and page size
is subtracted from 0 making a very large offset. The PAT code
in the kernel fails with a BUG_ON in reserve_memtype() checking
start >= end. The kernel needs to be fixed as well, but this
fallback path is wrong as well.
BUG=b:38211793
Change-Id: Idd5b22027633e5e1febd140336244f25a5304de4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7ad44eed08
Original-Change-Id: I32b0c15b2f1aa43fc57656d5d2d5f0e4e90e94ef
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19679
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506197
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Id63191e6f235622c0a93addf8a1afe97bb68bf78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a7092750b2
Original-Change-Id: I2fa1548ba1906db80ce3119eec58de9629f91ed7
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19296
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506224
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I01428c56e7e416f191c07278e1241ef43e7a5d9f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2a59a44416
Original-Change-Id: I0eff29b74d7df331dcbf2c25799eaae4911e54fc
Original-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/13749
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/506223
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
And don't link it. It's for ROMCC.
To make code happy that uses the ROMCC interface read_option(),
read_option_lowlevel() is ported to mc146818rtc.c along with
a message to use get_option() instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9e6b1aeca2824199bbdec7dcb2bee9306d0e46cb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c3da3fe1d3
Original-Change-Id: I54ea08de034766c8140b320075d36d5e811582fa
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19663
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506221
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Start-point is Gigabyte GA-G41M-ES2L.
This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.
Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).
Tested but fails:
* DDR3 (not implemented in coreboot).
Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieae7f68cadd2f41d94979c67267620272ed91319
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7d46e96ed7
Original-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18993
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506220
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not
supported). Should fix coverity issue 1375009. Remove a redundant
line that uses the variable `gfxsize` out of its scope and move the
variable declaration. Make sure the variable is always initialized,
drop unneeded error-handling for `get_option()` and sanitize the
read value instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: If91dd643c754fd049952065dba56bab731b7f449
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cfd433b96d
Original-Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19680
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/506219
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This board features a PATA port.
TESTED PATA drive works in SeaBIOS and OS.
BUG=none
BRANCH=none
TEST=none
Change-Id: I139e711a715782032c8eecb7f983aecd991c15b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dd2e35edc1
Original-Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19627
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/506218
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.
For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down
on mainboard, change internal pull up to none.
BUG=b:37998248
TEST=Boot up into OS and enter s0ix.
Change-Id: I65b001b851b9cec3cf6cbbc0d345127f57912dd8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 55cad16ca5
Original-Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19577
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/506217
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>