Even though the persistent CBMEM console is obviously awesome, there may
be cases where we only want to look at console output from the last boot.
It's easy to tell where one boot ends and another begins from the banner
message that coreboot prints at the start of every stage, but in order
to make it easier to find that point (especially for external tools),
let's put that functionality straight into the cbmem utility with a new
command line flag. Use the POSIX/libc regular expression API to find the
banner string for maximum compatilibity, even though it's kinda icky.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2f40e8b1bd67c4e7ff46c4c42fbfc3d9d176e0db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7b64a9f68
Original-Change-Id: Ic17383507a884d84de9a2a880380cb15b25708a1
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19497
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/494606
When using Wake On Voice &/or DCI, it requires xtal to be active during
low power idle.
With xtal being active in S0ix state power impact is 1-2 mW.
Hence set xtal bypass bit in CIR31C for low power idle entry.
TEST= Build with s0ix enable for Poppy. Boot to OS & verify that
bit 22 of CIR31C register is set. s0ix works.
Change-Id: Iaffe8defdc559fad908b852903db06725c1bf005
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c261c4b426
Original-Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19442
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/494050
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Add a configuration option to assign the binaryPI base address
for the ACPI registers. The binaryPI's assignment is determine
at build time and no run-time configuration is allowed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2fa71ebe07b6d20e0d7bd9302a35c17b543c00ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7f2c29b6d6
Original-Change-Id: Ida17022abfa6faceb0653c2cb87aacce4facef09
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19485
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494049
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Claim memory-mapped regions in the legacy area.
Claim an MMIO resource for the A000 and B000 segments, and reserved
resource for C000 through F000 segments.
These changes allow code and information to be retained in the event
unused regions get wiped.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d612d4fe69881609d42053496409c452e1014947)
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic5f61a63499db3b882f06ec4c8642519196d1a88
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a7ebd4e08
Original-Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19156
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/494048
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
cbgfx currently does not support portrait screen which height >width.
so add it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5efd25158e383f675131e0c6469b7af5147f908e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0e465456e
Original-Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19474
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494047
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Define a common area in CAR so that the storage data structures can be
shared between stages.
TEST=Build and run on Reef
Change-Id: I300059af6ef55d777eb9606c88f0a7f91d024b0c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 43d0d0d1f4
Original-Change-Id: I20a01b850a31df9887a428bf07ca476c8410d33e
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19300
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/494046
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Create Intel Common FAST_SPI Controller code.
This code contains the code for SPI initialization which has
the following programming -
* Get BIOS Rom Region Size
* Enable SPIBAR
* Disable the BIOS write protect so write commands are allowed
* Enable SPI Prefetching and Caching.
* SPI Controller register offsets in the common header fast_spi.h
* Implement FAST_SPI read, write, erase APIs.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifd05fa75ddd34ae5df48e4dee0618f30b8d23654
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89331cd4c8
Original-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18557
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/493985
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: I4dee11445385e7c6189593d8a09558e5cd8b7bac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 281ccca373
Original-Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19310
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493984
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: I355d6a04d31cb42a6113e32429a82eea0f924d0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2be2840a1d
Original-Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19309
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493983
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib359f8a42946da6a293b456ca087b899d53cf9cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0eb6cd8bd
Original-Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19307
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493982
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The AFCAdditional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
BUG=none
BRANCH=none
TEST=none
Change-Id: I912dc6f185b7df5e1b54aa90e64d7cfdb0bc0d63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0a4a4f7ae4
Original-Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19493
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/493981
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Based on Thinkpad x230 and schematics.
Verified by autoport.
USB debug port is the left front usb port
Thanks to Holger Levsen for the device.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iec695049d8bf2e115011b513af3d4eebe5b433a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db508565d2
Original-Change-Id: I97c8e01a3ce0577d7dc9e8df7d33db3b155fe3d6
Original-Tested-on: lenovo x1 carbon gen 1
Original-Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Original-Reviewed-on: https://review.coreboot.org/16994
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/493980
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Haswell, Broadwell, Baytrail, and Braswell ChromeOS devices'
FADT version were incorrectly set to 3, rather than the correct
ACPI_FADT_REV_ACPI_3_0. The incorrect value resulted in these
devices reporting compliance to ACPI 2.0, rather than ACPI 3.0.
This mirrors similar recent changes to SKL and APL SoCs.
Test: boot any affected device and check ACPI version reported
vai FADT header using OS-appropriate tools.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia974300bdc555a1062d2779083a19c3838f6cf78
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7ee81a4a01
Original-Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19498
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/493979
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Write vendor/device id to subsystem vendor/device id
if they are not provided.
BUG=none
BRANCH=none
TEST=none
Change-Id: I64ed5b8ce7f62968437aa4ca47d9f561eb88c2c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd891291ed
Original-Change-Id: I5027331a6adf9109767415ba22dfcb17b35ef54b
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19467
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/493978
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Enable audio:
* Add verb table for ALC286 & ALC298
* Enable virtual channel 1 for DmiVc1 & HdaVc1.
TEST= Build for kblrvp3 as well as kblrvp7. Boot to OS & verified
working of audio on both the boards.
Change-Id: I4f8dac51437704e61bf31ecb6f94224a1a4bf6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: af295495c2
Original-Change-Id: Id27e3cf585b93ed4131d7bf3d3b53d3f5404b18e
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18875
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/493976
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Enable/Disable the PCIe ports to match factory BIOS. The port #6
is used for PCIe on the M.2 connector which allows for NVMe SSDs
to function.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib16d60f88990c8481e2a2a5e180fa7d296910895
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cc558e6223
Original-Change-Id: I8058cbad3da651144545d588c0ae78c5f5e598ac
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19446
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/493974
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The Wildcat Point-LP Premium is handled the same as the Wildcat Point-LP,
but it wasn't supported by inteltool.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4128495cce8905d16d0213cea6df92fced1a0742
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1244a510f1
Original-Change-Id: I694514e1963f074582a3f5f81d63c20e7fa49189
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19445
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/493973
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Lint prevents my next commit which adds a new line to the table
so it's better to break all the > 80 character lines so it will be
consistent with the new line I'm about to add.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idf7498792710236ceebadb20748c37876864faa4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 085d87bcca
Original-Change-Id: Ic7ad0cb90e861cd830db1186225d4f839250792a
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19444
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/493972
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
input_underrun is defined but not used. A reasonably new compiler,
enabled warnings and warnings-as-error make the build break for no good
reason.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b3f117ef563d8828b09f5c09e91874925b685d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c854e943e0
Original-Change-Id: Ibeb7ba53aad5738938093ab7b34695c9c99c9afe
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19482
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/493971
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
It's standard practice in vboot that the FWID consists of
<board_name>.<version_number> (e.g. Google_Kevin.8785.57.0). In fact,
some tools rely on this and cut the string at the first dot to
separate the two.
The current Kconfig default in coreboot instead leads to ugly,
parser-breaking FWIDs like Google_Kevin4.5-1234-5678abcd. This patch
fixes that.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibbe8a40ccbcba8e4d448eb618b6291d43969a6b1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46f292f9bf
Original-Change-Id: I65cd5285c69e2e485d55a41a65d735f6a2291c16
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19487
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/493970
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.
BUG=b:37682566
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.
Change-Id: If9d2e7a0ecd0963a2e14dac32a28170938c670d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ac19c8629
Original-Change-Id: I4c748a316436001c5a33754084ab4a74243e21df
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19457
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493967
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Correct the default GBB_HWID to "ROWAN TEST 9387"
BRANCH=chromeos-2016.05
BUG=b:35774871
TEST=emerge-rowan coreboot chromeos-bootimage,
strings /build/rowan/firmware/image.bin | grep "ROWAN TEST"
and look for 9387 in output
Change-Id: I7851010305caf056958c8a6a328b0506bf2208cd
Signed-off-by: Patrick Berny <pberny@chromium.org>
Original-Commit-Id: bf84950154
Original-Change-Id: I7851010305caf056958c8a6a328b0506bf2208cd
Original-Signed-off-by: Patrick Berny <pberny@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19488
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/488127
Reviewed-by: YH Lin <yueherngl@chromium.org>
This needs some extra headers in amdk8/raminit.c that were otherwise
provided by that file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I93fc04d84b412f5db1c80766f28d1f31d8d8fe6a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 3eff00ec76
Original-Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19360
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490681
1. Select CONFIG_{TPM,TPM2} only when MOCK_SECDATA is not selected.
2. Provide tlcl_lib_init for mock TPM case.
BUG=b:37682566
TEST=Verified that when mock TPM is used, CONFIG_TPM is not set
anymore in coreboot config.
Change-Id: Ib704fe98cab5d6f13b5b7ea75d0ba242ed7e386a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 00f360e3f1
Original-Change-Id: If3bdd1528e153b164e9d62ee9cbcc4c3666b8b66
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19456
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490680
Create Intel Common ITSS code. This code currently only contains
the code for Interrupt initialization required in Bootblock phase.
More code will get added up in the subsequent phases.
BUG=none
BRANCH=none
TEST=none
Change-Id: I235ad1f657752906425ef739c69ec0fc06df7140
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: fcab4156c8
Original-Change-Id: I133294188eb5d1312caeafcb621fb650a7fab371
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19125
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490677
The SRS bit which is supposed to indicate reset button press
is non-functional. If it did work the system reset event it
was associated with is overly specific. Therefore, use the
warm reset status bit.
BUG=b:37687843
Change-Id: I60636f2ec24e4255a718fa3c087a55006411def2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: f39692ee3e
Original-Change-Id: I34dd09c03d2bca72da9a5cdf23121e0d0e621fa6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19484
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490676
It's come to attention that apollolake doesn't support a full retrain
on warm reset. Therefore force a cold reset when a full retrain is
requested in the non-S5 path.
BUG=b:37687843
Change-Id: Icea92953ccdb1c3233d1b5df5620b3f338eb0f46
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 9c86aafe5a
Original-Change-Id: If9a3de1fa8760e7bb2f06eef93a0deb9dbd3f047
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19483
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490675
Update default ODT config to have correct CA ODT settings as the
current defaults are incorrect for all the current apollolake designs.
All the current designs pull both A and B channels' LPDDR4 modules' ODT
pins to 1.1V. Therefore, the correct impedance setting needs to be
applied.
In order for the settings to take effect one needs to clear the
memory training cache in deployed systems. Trigger this by bumping
the memory setting version for the SoC.
If needed in the future support for allowing the override of this
setting from the mainboard should be straight forward. It's just not
necessary at this time.
BUG=b:37687843
TEST=BAT test, warm, reboot, S3 cycle test
Change-Id: Ie359847db7391798b2dce5301addecb3d95c88cc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: a3d13fbd69
Original-Change-Id: I9a2f7636b46492a9d08472a0752cdf1f86a72e15
Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19397
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/490674
On Chrome OS systems a memory setting change is needed to be deployed
without updating the FSP blob proper. Under such conditions one needs
to trigger retrain of the memory. For ease of use provide an option,
FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC
and mainboard memory setting version number into the FSP version
passed to the platform. The lower 8 bits of the FSP version are the
build number which in practice is normally 0. Use those 8 bits to
include the SoC and mainboard memory settings version. When FSP,
SoC, or mainboard memory setting number is bumped a retrain will be
triggered.
BUG=b:37687843
Change-Id: Ia0298efc1cb40716f808fcd2779a0d56ebec800a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: a3cecb2e71
Original-Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19452
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490673
Ironically enough, libsanitizer is notorious for creating "uninitialized
variable" warnings with different compiler versions than the one it's
shipping with.
Since we don't need it for building the real compiler, just skip it.
Fixes building our compilers using the gnat-gpl 2014 compilers.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib867e7f7bd8709659f7b49d76ba441904e15db14
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97a9df4f77
Original-Change-Id: I2130dfdf3eaf07d77cd70777419fc0ae4642b843
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19478
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/490083
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Add basic SMM support for Broadwell-DE SoC.
The code is mainly based on the SMM implementation of Broadwell with a
few differences:
- EMRR is now called PRMRR and the UNCORE part of it is not available
- SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space
- currently only SERIRQ-SMI has a handler
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic135fe932daed0cb63690d5675786933715c45a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97c0979bef
Original-Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19145
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490082
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
On Apollo Lake it was discovered that our current FADT implementation is
valid for ACPI version 3.0 but misses fields for ACPI version 5.0. We
run into booting issues with Windows 10 using version 5 in the FADT
header. In commit 2b8552f49bc3a7d0290f96a84b573669de396011
(intel/apollolake: Switch FADT to ACPI version 3.0) we go back to
version 3 for Apollo Lake. Skylake is now the last platform that uses
version 5 in FADT header.
BUG=none
BRANCH=none
TEST=none
Change-Id: I70041118196641bb6cbf90cd8d16723bdca9be59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00d250e228
Original-Change-Id: I2d0367fae5321dee4ccac417b7f99466f8973577
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19453
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490081
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The current implementation of the FADT structure is only ACPI 3.0 compliant.
Setting the version to ACPI 5.0 results in a corrupt FADT. Linux seems
to be able to deal with it but Windows 10 hangs in a really early stage
without any notification to the user.
If ACPI 5.0 is mandatory, the FADT structure needs to be adjusted to
match the specification. Therefore the members sleep_ctl and sleep_stat
needs to be added to FADT structure.
BUG=none
BRANCH=none
TEST=none
Change-Id: I009e765f7aabfc984af95e82c5cb632b81b54532
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27e6042bb7
Original-Change-Id: I51c7a7a84d10283f5c2a8a2c57257d53bbdee7ed
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19146
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490080
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Move the images around in the image stitching. This addresses
an issue found with PSP firmware loading on the Google Kahlee
mainboard.
Note firmware1 must come before firmware2 in the image or
the PSP will not allow APU to execute.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2d6d3cd1093c5dbe9fe57ce1ed03d30f8ef5be06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d81250cebc
Original-Change-Id: I85963fa93d6efd707cedfbc04b92d302ad5de3b1
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19170
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490078
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The new touchpad firmware uses i2c-hid instead of custom reporting
protocol. The touchpad also exposed another slave address (0x1e) for
kernel to communicate with the touchpad EC.
BUG=none
BRANCH=none
TEST=none
Change-Id: I717e1e1b5b739bef34c697e4f7ab4cb1b7593862
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 267e4a5824
Original-Change-Id: Iecaf14f7b8aed836120569e9ade9c3115bc00264
Original-Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Original-Reviewed-on: https://review.coreboot.org/19461
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490077
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Add a check for vboot when locating the binaryPI image.
There is currently an ordering problem using cbmem to locate the
image when vboot is present. Vboot inserts its locator into the
search process so that memory can be checked before flash is queried.
For the earliest calls using the wrapper, DRAM has not been set up
and cbmem not initialized in romstage. This change prevents an
endless loop when vboot searches cbmem.
This change has another side effect. When vboot is in effect, the
change forces the RO binaryPI to be used even when on either of the
RW paths. There is currently no ability to relocate the XIP image
for use in a RW region.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474)
BUG=none
BRANCH=none
TEST=none
Change-Id: If30b23954f97cc4565ff81b55ee3a9e4145be379
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca3815b4c5
Original-Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
AMD VBIOS option ROMs often modify themselves during initialization.
Check for the presence of a VBIOS at 0xc0000 before populating the
VFCT table. If a matching ROM is found, use it for the source of
the copy.
Tested on Gardenia (Stoney) variant by observing amdgpu driver's
dmesg output.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2c5d6487d22d551e07dbc0fd0da7d7e75a134c96
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f978cfd1a
Original-Change-Id: I5be7e1562bde51800c5b0e704c79812d85bcf362
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19383
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490075
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
