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UPSTREAM: src/include/device: Add PCIe root ports device ids
BUG=none
BRANCH=none
TEST=none
Change-Id: I59f286b1971973257bfe00db168dbf172e1a6ca5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fe6052c2e4
Original-Change-Id: Ic2df7fb1e4a3d3c52561b949c4b359ea59824387
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19664
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/506222
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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@ -2673,6 +2673,66 @@
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#define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56
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#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
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/* Intel PCIE device ids */
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2 0x9d11
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3 0x9d12
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4 0x9d13
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5 0x9d14
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6 0x9d15
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7 0x9d16
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8 0x9d17
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9 0x9d18
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10 0x9d19
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11 0x9d1a
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#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12 0x9d1b
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 0xa110
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2 0xa111
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3 0xa112
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4 0xa113
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5 0xa114
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6 0xa115
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7 0xa116
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8 0xa117
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9 0xa118
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10 0xa119
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11 0xa11a
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12 0xa11b
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13 0xa11c
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14 0xa11d
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15 0xa11e
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16 0xa11f
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17 0xa167
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18 0xa168
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19 0xa169
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#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20 0xa16a
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 0xa290
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2 0xa291
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3 0xa292
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4 0xa293
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5 0xa294
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6 0xa295
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7 0xa296
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8 0xa297
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9 0xa298
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10 0xa299
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11 0xa29a
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12 0xa29b
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13 0xa29c
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14 0xa29d
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15 0xa29e
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16 0xa29f
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17 0xa2e7
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18 0xa2e8
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19 0xa2e9
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20 0xa2ea
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21 0xa2eb
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22 0xa2ec
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23 0xa2ed
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#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24 0xa2ee
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/* Intel SATA device Ids */
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#define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03
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#define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07
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