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UPSTREAM: rockchip/rk3399: remove the delay for enabling SSC

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The hang was caused by deasserting the reset before, it had been delayed 20us
fixing the hang issue.

So we can remove this delay for now.

BUG=none
BRANCH=none
TEST=none

Change-Id: I12d09cd0d25974bbaffaf444f2af4697d85c2648
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2684efc492
Original-Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19699
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508772
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Caesar Wang 2017-05-16 08:39:40 +08:00 • committed by chrome-bot
parent 6fea4f61ba
commit 3674dae609
1 changed files with 0 additions and 5 deletions
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5
src/soc/rockchip/rk3399/clock.c
View file

@ -356,11 +356,6 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
{
u32 divval;
/*
* TODO find the root cause why is the delay needed, otherwise sometimes
* hang somewhere with reboot tests.
*/
udelay(30);
assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6);
/*