If deep Sx is enabled and prev sleep state was not S0, then if SUS
power was lost, it means that the platform had entered deep Sx. Add an
elog entry for deep Sx variant in this case.
BUG=b:38436041
TEST=Verified that elog entries are updated correctly:
Deep S5:
59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown
60 | 2017-05-19 10:39:09 | ACPI Enter | S5
61 | 2017-05-19 10:39:17 | System boot | 22
62 | 2017-05-19 10:39:17 | EC Event | Power Button
63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5
64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0
65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode
Deep S3:
66 | 2017-05-19 10:40:11 | ACPI Enter | S3
67 | 2017-05-19 10:40:16 | EC Event | Power Button
68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3
69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0
Normal S3:
77 | 2017-05-19 10:43:22 | ACPI Enter | S3
78 | 2017-05-19 10:43:39 | EC Event | Power Button
79 | 2017-05-19 10:43:39 | ACPI Wake | S3
80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0
Change-Id: Ic052854ef87fc88d4c25b6d14b8deb4fafe1f0fc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7941c96f8e
Original-Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19798
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513951
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is useful for debugging based on eventlog to identify if platform
entered normal or deep Sx.
BUG=b:38436041
Change-Id: Id63cf4d97126770e2a32a508d10ae5aff0d3e32b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 75ef6ec29e
Original-Change-Id: Ic7d8e5b8aafc07aed385fe3c4831ab7d29e1f890
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19797
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513950
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use SATA common code from soc/intel/common/block/sata
and clean up code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I26f5ca6de3d9cbaa09faac09bbc86ecf3402cde3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fd8e00092a
Original-Change-Id: Ib5d65f1afda6b2f8098f1c006623a48cf2690593
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19735
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510781
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add SATA code support in intel/common/block to initilalize
SATA controller, allocate resources and configure SATA port
status.
BUG=none
BRANCH=none
TEST=none
Change-Id: I53190966c44685573e636375444b471a6dec0f22
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1b1ecae0a4
Original-Change-Id: I42ec0059f7e311a232c38fef6a2e050a3e2c0ad3
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19734
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510780
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add PCIe code support under soc/intel/common/block
to initialize PCIe controller, allocate resources
and configure L1 substate latency.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifccff937795c9b1f710c527c0d3816b3e4731486
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2d689f9e0d
Original-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19665
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510778
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I72a8270841ec229a2e27be71f3a6b3262640e6f1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4bbfe57959
Original-Change-Id: I6e710b95cade0ea68f787f33c0070613d64b6da6
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19743
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510777
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since the conversion of this board to soc/broadwell in 0aa06cbf18
(wtm2: Convert to use soc/intel/broadwell), the NGI for this board
is not hooked up anywhere. Also, the code doesn't compile anymore.
BUG=none
BRANCH=none
TEST=none
Change-Id: I781280dad7477dd55788db2e487e20f4ec911b33
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 10326ba889
Original-Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19801
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/510773
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove guards and let the linker take care of it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I88864bb4de1b4185efb8ea8d42c61882dda1caf5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bb72852baf
Original-Change-Id: I96ad8002845082816153ca5762543768998a5619
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19744
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/510772
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This makes the code more readable since it avoids messing with two
dimensional arrays and needing remember what the indices mean.
Also introduces an unused coarse element which is 0 for all default
DLL settings on DDR2.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9ed31c150e8a3e3371f91027c62a76530b7dc99b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 27f0ca18bc
Original-Change-Id: I28377d2d15d0e6a0d12545b837d6369e0dc26b92
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19767
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/510771
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
All those boards do not have a serial port.
Don't attempt to decode the COMA/COMB IO range.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14fd3107b5fcf74c04d319b71971058e4f39736c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 93eac6a89d
Original-Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19571
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510770
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibed8577d19b6490545019d6bf142230c82fb181c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ac27d3688a
Original-Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19570
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510768
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a830468bbd1ddc8f0b815836234d9c0de019b5b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7565cf1a49
Original-Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19543
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510767
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Hides JEDEC steps using the RAM_SPEW macro.
Also hides a hexdump of SPDs.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9367a693d565076be2740948a892d0aa3bbdba1a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cfa2eaa4cc
Original-Change-Id: Ie2b484cf1f1d296823df0473e852d9d07ca20246
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18924
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510766
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ec6e0dbb1006be79b9a9412d5a60eb1c4b4590d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3db82be764
Original-Change-Id: I77aabf98ea48c6e8bdbe322f89666935f59a289a
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19760
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/510765
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This improves readability.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib654ffde2e45c442895b1d703b2e206ec063838d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: abc504f427
Original-Change-Id: Ib4387a4f4092053dab273191a73edb0ef31a79f6
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19691
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/510764
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
It is not really known why there is such a long delay, but it works
fine without it.
TESTED on ga-g41m-es2l.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7401ed84900a513ba2240e0c3b823aa46b5f7ec2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e729366d7a
Original-Change-Id: Idff5b978bbf161f8520d8000848e7b11c98c3945
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19514
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/510763
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b89a0b86082e5b57a53c5c7c6fd9fe0c9db6167
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1222162d12
Original-Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19513
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/510762
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Only board using this code was tyan s2735 which was removed in
f76de841f1 "[REMOVAL] tyan/s2735"
BUG=none
BRANCH=none
TEST=none
Change-Id: I75d2a72adf24ed89d74631f4101ab8b74c26f198
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bd23bd62b4
Original-Change-Id: I03a101adc1eedfa9669e0b44c54c2c6fa08bd5f2
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19507
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/509527
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=b:37712455
Change-Id: Ia5aa6665db0f8199de8d2cf363272d7e2b676363
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 365d97e938
Original-Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19766
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509526
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix SPD as per the vendor-provided data.
BUG=b:37712790
Change-Id: Id2054c54ec61c7bd3e9161c70506f45d31fd36d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 77be7339cd
Original-Change-Id: Ib87c316479f4a05e64ca4acb540d7aacfa7338e9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19749
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509525
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Define a new spi_flash_ops structure, move all spi flash operations to
this structure and add a pointer to this structure in struct spi_flash.
BUG=b:38330715
Change-Id: I29deaa94b0339972aa016b77a80344da6abadd06
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e2fc5e25f2
Original-Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19757
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509524
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it
so that drivers can use it outside spi_flash.c.
2. Make southbridge intel spi driver use spi_flash_generic_probe if
spi_is_multichip returns 0.
3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to
provide specialized probe functions. With this change, the specialized
spi flash probe functions are now associated with a particular spi
ctrlr structure and no longer disconnected from the spi controller.
BUG=b:38330715
Change-Id: I996ff78f75296cc5bc38b6e760545b9b7dd810c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a1491574ef
Original-Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19708
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509523
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Pointer to spi_slave structure can be passed in as const to spi flash
probe functions since the probe functions do not need to modify the
slave properties.
BUG=b:38330715
Change-Id: I817a51fc7b480f6532941fccd08a6179dbc14378
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bd9e32efdd
Original-Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19707
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509522
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove unused function declaration spi_fram_probe_ramtron.
BUG=b:38330715
Change-Id: I05900361e86178b297c29f57d7e907a237cf3452
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7863395ad1
Original-Change-Id: I05e6c5c2b97d6c8a726c0e443ad855f9bcb703f9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19706
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509521
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: Iea541abe70577dc357e8de4f62b5cd4b75c889e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 30221b45e0
Original-Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19705
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509520
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add a new member page_size to spi_flash structure so that the various
spi flash drivers can store this info in spi_flash along with the
other sizes (sector size and total size) during flash probe. This
removes the need to have {driver}_spi_flash structure in every spi
flash driver.
This is part of patch series to clean up the SPI flash and SPI driver
interface.
BUG=b:38330715
Change-Id: I1643c17f10226e943a3f94d4619f7e87f4b6777c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fc1a123aa7
Original-Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19704
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509519
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of storing spi flash device structure in spi flash driver, use
boot_device_spi_flash callback to obtain pointer to boot device spi
flash structure.
BUG=b:38330715
Change-Id: I83a384ce1b417869167d9dbeb38ed7a9900f0e11
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f422fd2c78
Original-Change-Id: Idd50b7644d1a4be8b62d38cc9239feae2215103c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19703
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509518
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This allows callers to retrieve handle to the boot device spi_flash structure.
BUG=b:38330715
Change-Id: Ica5e952ccca4f73dc35bfba31e4f9e0d880f0390
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 78bc6ddfd0
Original-Change-Id: I1c07327115e0449cbd84d163218da76a6fa2cea0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19726
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/509517
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested and working:
* HDD LED
* Booting GNU Linux 4.9 from HDD using SeaBios
* Booting GNU Linux 4.9 from USB using SeaBios
* Native GFX init
* All Fn function keys
* Speakers
* PCIe Wifi
* Camera
* WWAN
* Fan (Dynamic Thermal Managment)
* Flashing using internal programmer
* Dual memory DIMMs running at up to DDR3-1866
* AC events
* Touchpad, trackball and keyboard
* USB3 ports running at SuperSpeed
* Ethernet
* Headphone jack
* Speaker mute
* Microphone mute
* Volume keys
* Fingerprint sensor
* Lid switch
* Thinklight
* TPM (disable SeaBios CONFIG_TCGBIOS)
* CMOS options:
** power_on_after_fail
** reboot_counter
** boot_option
** gfx_uma_size
** usb_always_on
Untested:
* Booting Windows
* Hybrid graphics
* Docking station
* VGA
Broken:
* Wifi LED is always on
BUG=none
BRANCH=none
TEST=none
Change-Id: I8e9aa289a838691ce6edcddeb42cb4d1a865a609
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 714baa119b
Original-Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18011
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/509516
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Id27b75d20f71bdb6c532796944e62aea79d9174d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aeae34ffa4
Original-Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19551
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/509515
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Hide device 4 and device 7 if disabled.
Allows devicetree settings to take effect.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4f94c1f37cc85c293e2e5d8f41545d67ae11a9de
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ecd4be8114
Original-Change-Id: I64a19e2bbdb1640e1d732f6e4486f73cbb0bda81
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19689
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/509514
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The 'cbmem -1' flag that cuts off console output before the last boot
will ignore content from earlier stages if it was truncated due to lack
of pre-CBMEM console space. This patch makes the "log truncated" message
more specific and adds it as an additional cut-off marker to 'cbmem -1'
to counteract that problem.
Also raise the log level of the coreboot banner one step to BIOS_NOTICE
to make it more likely to be included in the output for 'cbmem -1' to
find. (I believe NOTICE is reasonable but I wouldn't want to go as far
as WARN which should be reserved for actual problems. Of course this is
not ideal, but then again, our whole log-level system really isn't... it
would be better if we could make it always print a banner to the CBMEM
console without affecting the UART at the same time, but that would
require a larger amount of work.)
BUG=none
BRANCH=none
TEST=none
Change-Id: I71f5ae9e44509608d3c47edcb4a7c869d0d650db
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d906bb68c3
Original-Change-Id: I58288593dfa757e14f4a9da4ffa7e27b0b66feb9
Original-Reported-by: https://ticket.coreboot.org/issues/117
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19720
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509513
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This reverts commit 6434755b96.
Revert the revert to get the touchpad ID ready for
the new touchpad firmware again.
BUG=b:35581264
BRANCH=none
TEST=none
Change-Id: I0c70f2c7c844d9199b9098783c24a6a0460263cc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506785
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
We have several different UART implementations of which three support a
timeout when receiving characters. In all of these three implementations
there is a bug where when the timeout is hit the last received character
will be returned instead of the needed 0.
The problem is that the timeout variable i is decremented after it has
been checked in the while-loop. That leads to the fact that when the
while-loop is aborted due to a timeout i will contain 0xffffffff and not
0. Thus in turn will fool the following if-statement leading to wrong
return value to the caller in this case. Therefore the caller will see a
received character event if there is none.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b846abcdbc3b0e4777ff541dbb0ae7aa9f5f8d5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 43314ffae5
Original-Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19731
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508780
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6ab4e00cbae38bbbc6f8633a3d77944a25a6ecdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e87564ffe7
Original-Change-Id: I0c375e5da0dfef6cef0c50272356cd32a87b1ff6
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19346
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508779
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie72f645e841d758ad4a275c39111c3a785ddd883
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 61be3603f4
Original-Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19328
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/508778
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
AGESA and binaryPI boards have no easy way to determine correct
cbmem_top() location early enough when GFXUMA is enabled, so they
will use these functions with EARLY_CBMEM_INIT as well.
At the end of AmdInitPost() the decisions of UMA base and size
have not been written to hardware yet. The decisions are stored
inside AGESA heap object we cannot locate from coreboot proper
until after AmdInitEnv().
Modify code such that weak backup functions are only defined
for LATE_CBMEM_INIT; they are somewhat troublesome to handle.
BUG=none
BRANCH=none
TEST=none
Change-Id: I507ef40b77f20c76b3178654c397a4130092240d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a7dd645594
Original-Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19306
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/508776
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
In the intel/common/block
* Move I2C common code from intel/common to intel/common/block.
* Split the code into common, early init and post mem init stages and put it
in lpss_i2c.c, i2c_early.c and i2c.c respectively.
* Declare functions for getting platform specific i2c bus config and
mapping bus to devfn and vice versa, that have to be implemented by SoC.
In skylake/apollolake
* Stop using code from soc/intel/common/lpss_i2c.c.
* Remove early i2c initialization code from bootblock.
* Refactor i2c.c file to implement SoC specific methods
required by the I2C IP block.
BUG=none
BRANCH=none
TEST=none
Change-Id: I82264b8a57b3cfd8be2281b7f3f32da158d0ac32
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ae6a4b6d3c
Original-Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19468
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508775
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
TEST=Boot from scarlet, and mipi panel works
Change-Id: I28ae05e1d3681a6012da80cf2e2dae196110559c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 36b09b8a6c
Original-Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19700
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508774
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch configures clock for mipi and then
adds mipi driver for support innolux-p079zca
mipi panel in rk3399 scarlet.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7e18b13b1403cb731aa8b5bd214bd35fd5f96637
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fe122d4dfc
Original-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19477
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508773
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The hang was caused by deasserting the reset before, it had been delayed 20us
fixing the hang issue.
So we can remove this delay for now.
BUG=none
BRANCH=none
TEST=none
Change-Id: I12d09cd0d25974bbaffaf444f2af4697d85c2648
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2684efc492
Original-Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19699
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508772
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Program eMMC DLL settings for mc_apl1 mainboard, after that system can
boot up with eMMC successfully.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ife34e1b5079eca8e51f2270439dbe05d613ed688
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c7ccb6b29f
Original-Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19712
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/508771
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The mainboard siemens/mc_apl1 uses an external I/O port for console
output. For this reason we need to activate the 8250 LPC UART.
BUG=none
BRANCH=none
TEST=none
Change-Id: I32e68e06a64308bf56010ce2e8e48ba42fd788b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ae10ec6239
Original-Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19694
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508770
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
