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UPSTREAM: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR

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Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"

BUG=none
BRANCH=none
TEST=none

Change-Id: I6a830468bbd1ddc8f0b815836234d9c0de019b5b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7565cf1a49
Original-Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19543
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510767
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Patrick Rudolph 2017-05-03 18:38:21 +02:00 • committed by chrome-bot
parent 3b6a0a93ba
commit ec3fb41d87
2 changed files with 4 additions and 0 deletions
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3
src/southbridge/intel/bd82x6x/finalize.c
View file

@ -65,6 +65,9 @@ void intel_pch_finalize_smm(void)
/* GEN_PMCON Lock */
pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2));
/* ETR3: CF9GR Lockdown */
pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
pci_write_config32(PCI_DEV(0, 27, 0), 0x74,

1
src/southbridge/intel/bd82x6x/pch.h
View file

@ -144,6 +144,7 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define ETR3 0xac
#define ETR3_CWORWRE (1 << 18)
#define ETR3_CF9GR (1 << 20)
#define ETR3_CF9LOCK (1 << 31)
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)