Commit graph

705 commits

Author SHA1 Message Date
Carl-Daniel Hailfinger
03dca375db Right now, our Kconfig files in the mainboard/ directory in the v3 tree
are not exactly in the best shape.
- MAINBOARD_NAME is claimed to be the mainboard name, but it is used 
  exclusively as mainboard directory.
- MAINBOARD_NAME is set in mainboard/$VENDOR/$BOARD/Kconfig to
  $VENDOR/$BOARD, but mainboard/$VENDOR/Kconfig already hardcodes
  $VENDOR/$BOARD as board path.
- MAINBOARD_NAME has a help text which will never be displayed to
  the user.

The diffstat is encouraging: A total of 200 lines have been
removed completely.

Per-board Kconfig files have been deleted, the remnants making sense
have been merged into per-vendor Kconfig files and the never-shown help
texts have been removed.

If there are ever some real per-board options and not just tricks to
make the makefiles behave, we can resurrect the per-board Kconfig files.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@705 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:40:22 +00:00
Ronald G. Minnich
ea5e263466 move amdk8 to amd/k8 per IRC discussion
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@704 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:26:06 +00:00
Ronald G. Minnich
178f27bc31 v3: Clean up a Kconfig value and fixup K8 CAR defines to get CONFIG_ values
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@703 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:16:45 +00:00
Ronald G. Minnich
06ced7c09a The m57sli almost builds. It's pretty empty. The dtc is not run .
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@702 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:03:22 +00:00
Ronald G. Minnich
935c99a3a9 minor include stuff.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@701 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 16:59:09 +00:00
Ronald G. Minnich
2f5d7b66a9 1. fix dtc to properly put @x,y in hex, not decimal.
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-30 15:08:25 +00:00
Ronald G. Minnich
96914e1655 1. geodelx.c: cover case of unterminated DRAM by adding a terminated
parameter to two functions. 
2. geodelx.h: define DRAM_TERMINATED and DRAM_UNTERMINATED constants
3. dbe62/initram.c: move to auto PLL control, so set MANUALCONF to 0
4. all other initram.c: set up calls to cpu_reg_init with proper 
   TERMINATED/UNTERMINATED constants. 

builds for dbe62. The auto PLL strapping is tested and works. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@699 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-29 15:54:46 +00:00
Ronald G. Minnich
bc75f3349d Add names for control bits.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>



Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@698 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-25 19:44:08 +00:00
Carl-Daniel Hailfinger
b1596f216b Rename mainboard_part_number to mainboard_name in various places. This
is the logical continuation of r416 which happened a year ago.

As an added bonus, we now have consistent naming again, making grepping
the source for dts properties possible.

Build tested on all targets. Patch attached for Gmail users.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@697 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-20 21:05:25 +00:00
Marc Jones
33654d8321 There was a programming error which made most USB port4 setup wrong. This
patch uses byte pointer and the MMIO read and write functions. 

Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@696 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-14 23:04:48 +00:00
Uwe Hermann
72d1721ea1 Fix a build-error for the ADL MSM800SEV.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@695 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-12 12:03:55 +00:00
Carl-Daniel Hailfinger
a4b90bacf4 Makes mainboard-vendor naming more consistent.
mainboard-name naming has been postponed because it's not clear what the
real name should be.

Generated code is identical to the state before the patch.
Compile tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@694 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-11 12:33:46 +00:00
Carl-Daniel Hailfinger
d9e875537b Move default mainboard vendor/subsystem from Kconfig to dts.
Compile tested including boundary cases.
Runtime tested on dbe62 by Ron. Works fine.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@693 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-09 21:21:39 +00:00
Carl-Daniel Hailfinger
0f05bd42db - Clean up Geode companion chip CS5536 code.
- Eliminate a few redundant dev_find_pci_device() calls.
- Fix a compile warning intruduced in r689.

This should be an equivalence transformation.

Build tested on norwich, db800, alix.1c, alix.2c3, dbe62, dbe61.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@692 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-03 19:42:05 +00:00
Patrick Georgi
ef90e728ab Implements console and serial lbtable records compatible to cbv2 as of r3396
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@691 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-29 06:43:01 +00:00
Patrick Georgi
ae2520e4bd Order libraries last on the command line when
building kconfig and lxdialog, so that their
content is used to resolve unknown symbols even
when they are static libraries.

Also fix HOST_LOADLIBS typo.

Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@690 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-06 20:47:42 +00:00
Ronald G. Minnich
e1ef6d2dc8 This change adds some debug prints, and a comment warning to dts on cs5536.
Most importantly it fixes a simple programming error which made it so most of
the sets on the USB were not doing anything. The bug is also in V2.

With this fix, the DBE62 USB ports all work!

If someone clones the fix to V2, it will also fix V2. Or, we can just convince
you to move forward to V3 :-)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@689 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-04 14:36:35 +00:00
Ronald G. Minnich
dba27d1bcd This patch gets usb port 3 on dbe62 working and sets up a dts-based way to map
USB EHCI power control registers to power enables pins 1 and 2. 

Why doesn't port 4 work? Who knows. That's a problem for another day. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>


Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@688 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-03 15:22:16 +00:00
Mart Raudsepp
11490d2898 artecgroup/dbe61: Set up 4MB mode for LPC dongle
This way we can fit a kernel and initramfs on the dongle's free ~3.75MB space
and have a debug system bootable right from inside the dongle. The start
address of the dongle is mem@0xffc00000 for FILO with 4MB minus ROM area
available.

This should be a no-op when not booting from the dongle.

The same change was done to artecgroup/dbe62/stage1.c in rev660.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@687 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-28 01:00:36 +00:00
Mart Raudsepp
c26b7ea48e artecgroup/dbe61: Set up some video memory, as the device has VGA output.
This allows me to have a working coreinfo payload on DBE61 with coreboot-v3.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@686 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-28 00:58:59 +00:00
Carl-Daniel Hailfinger
9700b1e3b6 Fix a typo in r684 which caused compilation to fail. Trivial.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@685 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-23 19:59:43 +00:00
Carl-Daniel Hailfinger
6198dc8271 Print current and wanted LZMA scratchpad size in the decompression
routine. That allows people to either adjust compression parameters
or scratchpad size.
Having a similar check during build time would be nice.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@684 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-23 19:56:50 +00:00
Mart Raudsepp
58a87f61c3 doxy: Fix doxygen build by renaming Doxyfile file from .LinuxBIOS to .coreboot, as the reference in build system was already changed to Doxyfile.coreboot back in January 27th
This makes doxygen documentation building work again.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@683 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-22 15:52:33 +00:00
Ronald G. Minnich
dc231a7041 This is the fix for MFGPT on those boards which have a cs5536 and ALSO
have a superio.
With this patch, alix1c and MFGPT work fine. Still need to test on Alix2c3, but it
is likely it will work.

Thanks to Marc and Jordan for this one.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@682 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 21:48:28 +00:00
Ronald G. Minnich
573d88e61d The Geode has MSRs. LOTS of MSR. I get confused trying to find them.
This program was originally written for OLPC and GX, and dumps all LX
registers used in coreboot. 
I have preserved the indent structure since that gives some idea of the
scope of variables. 
Of particular interest are the GLD variables, since they are always
listed as offsets in the manuals, 
and computing the actual number (for use in rdmsr etc.) can be really
tricky. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@681 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 16:12:41 +00:00
Ward Vandewege
e31836b6af This puts USB and eth2 on IRQ 11 (eth1 was already on IRQ 11). This makes the
kernel much happier.

As Marc suggested, having these devices all on the same IRQ seems to be fine.
I've tested performance - I get 11MB/sec copying data from eth2 to eth1, as
well as from eth2 to eth0 (which is on a different IRQ). That's 90% of
wirespeed which is what I'd expect to see.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@680 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 14:00:57 +00:00
Mart Raudsepp
e21fe8215f artecgroup/dbe61: Sync irq_tables with dbe62 code to fix compilation and have a chance of working properly.
In theory the routing settings should work fine the same in DBE61 and DBE62.
Some of the settings are left as in v2 until testing can be done once RAM setup is fixed.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@679 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 06:48:15 +00:00
Ronald G. Minnich
ed9cd01e22 Changed erroneous write config 8 to write config 32
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@678 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-08 14:51:40 +00:00
Carl-Daniel Hailfinger
4ab20cb518 Move CS5536 IDE configuration into a separate dts and its own PCI device.
Fix dbe62 IDE/NAND selection.

Build-tested on db800, norwich, dbe62, alix.1c, alix.2c3.
No additional breakage for dbe61.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@677 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-07 23:21:55 +00:00
Mart Raudsepp
899f4292c9 artecgroup/dbe62: Fix up the irq table checksum
Trivial change

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@676 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-05 13:59:01 +00:00
Ward Vandewege
7eebe3ffb2 00:0f.3 is the audio device, not usb. Also some whitespace cleaning.
All of this is applies to comments only.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@675 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-04 20:08:31 +00:00
Mart Raudsepp
a54afb5674 artecgroup/dbe62: Set up video memory
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@674 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-03 03:49:30 +00:00
Mart Raudsepp
6757b7b2c0 artecgroup/dbe62: Route ethernet adapter IRQ correctly and reduce interrupt contention problems by using different IRQs for all the interrupt lines
This makes the network adapter work fully, and reduces problems on high traffic (e.g kernel oopses on fsck run over USB 2.0 HDD)
Many thanks for Peter Stuge for a lot of IRQ related help.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@673 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-03 02:03:33 +00:00
Ronald G. Minnich
f7e9a631ef Add back in missing line of DRAM info.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@672 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-30 04:14:52 +00:00
Ronald G. Minnich
310f1af306 Rework Geode LX RAMinit DIMM size formula to be more
understandable. Added benefit is complaining loudly for
unsupported 2 GB DIMM size.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Tested on the dbe62 up to and including Etherboot. 

Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@671 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-30 04:12:56 +00:00
Stefan Reinauer
dbc8b4a8e4 remove typo... (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@670 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-29 11:49:42 +00:00
Ronald G. Minnich
b585710bc2 properly align bridge resources.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
Tested on v3 and 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

This patch also (accidently) includes 
a simple fix for the null pointer reference problem. I had forgotten that 
the fix was in there, but I will include it here and hope no one is too upset about 
its inclusion. 



git-svn-id: svn://coreboot.org/repository/coreboot-v3@669 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-29 03:52:57 +00:00
Mart Raudsepp
b73f9f86c0 mainboard/artecgroup: Clarify Kconfig help for Artec Group DBE61 and DBE62
* Linutop 2 is not a DBE62
* ThinCan is the trademarked brand name for the thin client line, not an alternate "also known as" name

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@668 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-27 02:50:07 +00:00
Ward Vandewege
e9f7d1de66 Fix code warning - val.type is a char, and NULL is not.
Thanks to Carl-Daniel for spotting this one, and Segher for providing the solution right away.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@667 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-26 12:05:08 +00:00
Stefan Reinauer
479ca87df3 Fix vga initialization for qemu virtual graphics adapter.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@666 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-24 20:45:57 +00:00
Ward Vandewege
df60eea846 The default config (used by buildrom) should not have a payload defined.
Buildrom handles that.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@665 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-19 14:29:56 +00:00
Mart Raudsepp
a4c9dc577b artecgroup/dbe62: This device has NAND instead of IDE - enable it in dts
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@664 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-18 07:37:43 +00:00
Ward Vandewege
b68f1ac979 Add pcengines alix.2c3 support.
There is still one outstanding issue - eth2 and the USB ports fight over IRQs.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@663 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-17 17:27:13 +00:00
Ward Vandewege
fd4ef4a84a Add unwanted_vpci parsing to AMD's cs5536 southbridge.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@662 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-17 16:30:27 +00:00
Ward Vandewege
a53508b751 Add generic array support to the coreboot dts output code.
This is necessary for the 'unwanted_vpci' field on geode-based boards.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@661 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-17 16:13:58 +00:00
Ward Vandewege
df28d2058a artecgroup/dbe62: Set up 4MB mode for LPC dongle
This way we can fit a kernel and initramfs on the dongle's free ~3.75MB space
and have a debug system bootable right from inside the dongle. The start
address of the dongle is mem@0xffc00000 for FILO with 4MB minus ROM area
available.

This should be a no-op when not booting from the dongle.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@660 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-16 21:34:56 +00:00
Carl-Daniel Hailfinger
5a19770667 northbridge/amd/geodelx/raminit.c:auto_size_dimm() checks for the
mathematically impossible condition of a value being above and below the
specified range at the same time. Change it to check for out-of-range.
arch/x86/geodelx/geodelx.c:set_delay_control() is missing a break, it
will keep going and mess up DRAM timings.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Both changes look right to me.
Acked-by: Marc Jones <marc.jones@amd.com>


The raminit in v2 was fixed in r2899 | rminnich | 2007-10-26 with this
log:
> The lxraminit change fixes a bug (&& used instead of ||) [...]
> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
> Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@659 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-16 16:40:45 +00:00
Myles Watson
c4a9590044 This very short patch fixes nrv2b compression in lar.
It also fixes lzma compression in lar to fix the silent memory
corruption that was possible when files didn't compress well.

It adds some comments to both files and the file that calls them.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@658 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-14 14:19:09 +00:00
Stefan Reinauer
7920e8a96a retrieve option roms from lar.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@657 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-05 20:18:47 +00:00
Ward Vandewege
2dc8f8ec2f We need a defconfig file for the alix.1c under v3.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@656 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-05 00:09:29 +00:00