mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Add pcengines alix.2c3 support.
There is still one outstanding issue - eth2 and the USB ports fight over IRQs. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@663 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ward Vandewege
parent
fd4ef4a84a
commit
b68f1ac979
9 changed files with 624 additions and 0 deletions
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@ -35,7 +35,19 @@ config BOARD_PCENGINES_ALIX1C
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help
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PC Engines ALIX1.C.
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config BOARD_PCENGINES_ALIX2C3
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bool "ALIX.2C3"
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select ARCH_X86
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select CPU_AMD_GEODELX
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select OPTION_TABLE
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select NORTHBRIDGE_AMD_GEODELX
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select SOUTHBRIDGE_AMD_CS5536
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select PIRQ_TABLE
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help
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PC Engines ALIX.2C3.
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endchoice
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source "mainboard/pcengines/alix1c/Kconfig"
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source "mainboard/pcengines/alix2c3/Kconfig"
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28
mainboard/pcengines/alix2c3/Kconfig
Normal file
28
mainboard/pcengines/alix2c3/Kconfig
Normal file
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@ -0,0 +1,28 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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## Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config MAINBOARD_NAME
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string
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default pcengines/alix2c3
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depends BOARD_PCENGINES_ALIX2C3
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help
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This is the default mainboard name.
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33
mainboard/pcengines/alix2c3/Makefile
Normal file
33
mainboard/pcengines/alix2c3/Makefile
Normal file
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@ -0,0 +1,33 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
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INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/northbridge/amd/geodelx/raminit.c \
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$(src)/arch/x86/geodelx/geodelx.c
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STAGE2_MAINBOARD_OBJ =
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$(obj)/coreboot.vpd:
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$(Q)printf " BUILD DUMMY VPD\n"
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$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
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75
mainboard/pcengines/alix2c3/cmos.layout
Normal file
75
mainboard/pcengines/alix2c3/cmos.layout
Normal file
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@ -0,0 +1,75 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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440 1 e 0 dcon_present
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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96
mainboard/pcengines/alix2c3/defconfig
Normal file
96
mainboard/pcengines/alix2c3/defconfig
Normal file
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@ -0,0 +1,96 @@
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#
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# Automatically generated make config: don't edit
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# coreboot version: 3.0."656"'
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# Wed Apr 9 20:59:03 2008
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#
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#
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# General setup
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#
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# CONFIG_EXPERIMENTAL is not set
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# CONFIG_EXPERT is not set
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CONFIG_LOCALVERSION=""
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#
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# Mainboard
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#
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# CONFIG_VENDOR_ADL is not set
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# CONFIG_VENDOR_AMD is not set
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# CONFIG_VENDOR_ARTECGROUP is not set
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# CONFIG_VENDOR_EMULATION is not set
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CONFIG_VENDOR_PCENGINES=y
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CONFIG_MAINBOARD_NAME="pcengines/alix2c3"
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# CONFIG_BOARD_PCENGINES_ALIX1C is not set
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CONFIG_BOARD_PCENGINES_ALIX2C3=y
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# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
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CONFIG_COREBOOT_ROMSIZE_KB_512=y
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# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
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# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
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CONFIG_COREBOOT_ROMSIZE_KB=512
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CONFIG_ARCH_X86=y
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CONFIG_ARCH="x86"
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CONFIG_CPU_AMD_GEODELX=y
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CONFIG_OPTION_TABLE=y
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CONFIG_PIRQ_TABLE=y
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CONFIG_CARBASE=0x80000
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CONFIG_CARSIZE=0x8000
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#
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# Compression
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#
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CONFIG_COMPRESSION_LZMA=y
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# CONFIG_COMPRESSION_NRV2B is not set
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CONFIG_DEFAULT_COMPRESSION_LZMA=y
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# CONFIG_DEFAULT_COMPRESSION_NRV2B is not set
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# CONFIG_DEFAULT_COMPRESSION_NONE is not set
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#
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# Console
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#
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CONFIG_CONSOLE=y
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CONFIG_CONSOLE_LOGLEVEL_8=y
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# CONFIG_CONSOLE_LOGLEVEL_7 is not set
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# CONFIG_CONSOLE_LOGLEVEL_6 is not set
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# CONFIG_CONSOLE_LOGLEVEL_5 is not set
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# CONFIG_CONSOLE_LOGLEVEL_4 is not set
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# CONFIG_CONSOLE_LOGLEVEL_3 is not set
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# CONFIG_CONSOLE_LOGLEVEL_2 is not set
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# CONFIG_CONSOLE_LOGLEVEL_1 is not set
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# CONFIG_CONSOLE_LOGLEVEL_0 is not set
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CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
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CONFIG_CONSOLE_SERIAL=y
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CONFIG_CONSOLE_SERIAL_COM1=y
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# CONFIG_CONSOLE_SERIAL_COM2 is not set
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CONFIG_CONSOLE_SERIAL_115200=y
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# CONFIG_CONSOLE_SERIAL_57600 is not set
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# CONFIG_CONSOLE_SERIAL_38400 is not set
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# CONFIG_CONSOLE_SERIAL_19200 is not set
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# CONFIG_CONSOLE_SERIAL_9600 is not set
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CONFIG_CONSOLE_BUFFER=y
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#
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# Devices
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#
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CONFIG_PCI_OPTION_ROM_RUN=y
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# CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set
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CONFIG_PCI_OPTION_ROM_RUN_VM86=y
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# CONFIG_PCI_OPTION_ROM_RUN_NONE is not set
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# CONFIG_MULTIPLE_VGA_INIT is not set
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# CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set
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#
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# Power management
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#
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CONFIG_NORTHBRIDGE_AMD_GEODELX=y
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CONFIG_SOUTHBRIDGE_AMD_CS5536=y
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CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32
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#
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# Payload
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#
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# CONFIG_PAYLOAD_ELF_LOADER is not set
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CONFIG_PAYLOAD_ELF=y
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# CONFIG_PAYLOAD_NONE is not set
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CONFIG_PAYLOAD_FILE="../payload.elf"
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# CONFIG_ZERO_AFTER_PAYLOAD is not set
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54
mainboard/pcengines/alix2c3/dts
Normal file
54
mainboard/pcengines/alix2c3/dts
Normal file
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@ -0,0 +1,54 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/{
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mainboard-vendor = "PC Engines";
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mainboard-name = "ALIX.2C3";
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cpus { };
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apic@0 {
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/config/("northbridge/amd/geodelx/apic");
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};
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domain@0 {
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/config/("northbridge/amd/geodelx/domain");
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pci@1,0 {
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/config/("northbridge/amd/geodelx/pci");
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};
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pci@15,0 {
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/config/("southbridge/amd/cs5536/dts");
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enable_ide = "1";
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/* Interrupt enables for LPC bus.
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* Each bit is an IRQ 0-15. */
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lpc_serirq_enable = "0x000010da";
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/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
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lpc_serirq_polarity = "0x0000EF25";
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/* 0:continuous 1:quiet */
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lpc_serirq_mode = "1";
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/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
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* See virtual PIC spec. */
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enable_gpio_int_route = "0x0D0C0700";
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/* COM1 settings */
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com1_enable = "1";
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com1_address = "0x3f8";
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com1_irq = "4";
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/* this board does not really have vga; disable it (pci device 00:01.1) */
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unwanted_vpci = < 80000900 0 >;
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};
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};
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};
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165
mainboard/pcengines/alix2c3/initram.c
Normal file
165
mainboard/pcengines/alix2c3/initram.c
Normal file
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@ -0,0 +1,165 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <amd_geodelx.h>
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#include <northbridge/amd/geodelx/raminit.h>
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#include <spd.h>
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#define MANUALCONF 0 /* Do automatic strapped PLL config */
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#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
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#define PLLMSRLO 0x02000030
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#define DIMM0 ((u8) 0xA0)
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#define DIMM1 ((u8) 0xA2)
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|
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/* The part is a Hynix hy5du121622ctp-d43.
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*
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* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
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* Hynix
|
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* DDR SDRAM (5D)
|
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* VDD 2.5 VDDQ 2.5 (U)
|
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* 512M 8K REFRESH (12)
|
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* x16 (16)
|
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* 4banks (2)
|
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* SSTL_2 (2)
|
||||
* 4th GEN die (C)
|
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* Normal Power Consumption (<blank> )
|
||||
* TSOP (T)
|
||||
* Single Die (<blank>)
|
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* Lead Free (P)
|
||||
* DDR400 3-3-3 (D43)
|
||||
*/
|
||||
|
||||
struct spd_entry {
|
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u8 address;
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u8 data;
|
||||
};
|
||||
|
||||
/* Save space by using a short list of SPD values used by Geode LX Memory init */
|
||||
static const struct spd_entry spd_table[] = {
|
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{SPD_ACCEPTABLE_CAS_LATENCIES, 0x10},
|
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{SPD_BANK_DENSITY, 0x40},
|
||||
{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff},
|
||||
{SPD_MEMORY_TYPE, 7},
|
||||
{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */
|
||||
{SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */
|
||||
{SPD_NUM_BANKS_PER_SDRAM, 4},
|
||||
{SPD_PRIMARY_SDRAM_WIDTH, 8},
|
||||
{SPD_NUM_DIMM_BANKS, 1}, /* ALIX.2C3 is 1 bank. */
|
||||
{SPD_NUM_COLUMNS, 0xa},
|
||||
{SPD_NUM_ROWS, 3},
|
||||
{SPD_REFRESH, 0x3a},
|
||||
{SPD_SDRAM_CYCLE_TIME_2ND, 60},
|
||||
{SPD_SDRAM_CYCLE_TIME_3RD, 75},
|
||||
{SPD_tRAS, 40},
|
||||
{SPD_tRCD, 15},
|
||||
{SPD_tRFC, 70},
|
||||
{SPD_tRP, 15},
|
||||
{SPD_tRRD, 10},
|
||||
};
|
||||
|
||||
/**
|
||||
* Given an SMBUS device, and an address in that device, return the value of SPD
|
||||
* for that device. In this mainboard, the only one that can return is DIMM0.
|
||||
* @param device The device number
|
||||
* @param address The address in SPD rom to return the value of
|
||||
* @returns The value
|
||||
*/
|
||||
u8 spd_read_byte(u16 device, u8 address)
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||||
{
|
||||
int i;
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||||
/* returns 0xFF on any failures */
|
||||
u8 ret = 0xff;
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||||
|
||||
printk(BIOS_DEBUG, "spd_read_byte dev %04x", device);
|
||||
if (device == DIMM0) {
|
||||
for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
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||||
if (spd_table[i].address == address) {
|
||||
ret = spd_table[i].data;
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||||
break;
|
||||
}
|
||||
}
|
||||
if (i == ARRAY_SIZE(spd_table))
|
||||
printk(BIOS_DEBUG, " addr %02x does not exist in SPD table",
|
||||
address);
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Placeholder in case we ever need it. Since this file is a
|
||||
* template for other motherboards, we want this here and we want the
|
||||
* call in the right place.
|
||||
*/
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup */
|
||||
}
|
||||
|
||||
/**
|
||||
* main for initram for the PC Engines Alix.2c3. It might seem that you
|
||||
* could somehow do these functions in, e.g., the cpu code, but the
|
||||
* order of operations and what those operations are is VERY strongly
|
||||
* mainboard dependent. It's best to leave it in the mainboard code.
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Hi there from stage1\n");
|
||||
post_code(POST_START_OF_MAIN);
|
||||
|
||||
system_preinit();
|
||||
printk(BIOS_DEBUG, "done preinit\n");
|
||||
|
||||
mb_gpio_init();
|
||||
printk(BIOS_DEBUG, "done gpio init\n");
|
||||
|
||||
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
|
||||
printk(BIOS_DEBUG, "done pll reset\n");
|
||||
|
||||
cpu_reg_init(0, DIMM0, DIMM1);
|
||||
printk(BIOS_DEBUG, "done cpu reg init\n");
|
||||
|
||||
sdram_set_registers();
|
||||
printk(BIOS_DEBUG, "done sdram set registers\n");
|
||||
|
||||
sdram_set_spd_registers(DIMM0, DIMM1);
|
||||
printk(BIOS_DEBUG, "done sdram set spd registers\n");
|
||||
|
||||
sdram_enable(DIMM0, DIMM1);
|
||||
printk(BIOS_DEBUG, "done sdram enable\n");
|
||||
|
||||
/* Check low memory */
|
||||
/*ram_check(0x00000000, 640*1024); */
|
||||
|
||||
printk(BIOS_DEBUG, "stage1 returns\n");
|
||||
return 0;
|
||||
}
|
||||
109
mainboard/pcengines/alix2c3/irq_tables.h
Normal file
109
mainboard/pcengines/alix2c3/irq_tables.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <pirq_routing.h>
|
||||
|
||||
/* Number of slots and devices in the PIR table */
|
||||
#define IRQ_SLOT_COUNT 6
|
||||
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 9
|
||||
#define PIRQB 10
|
||||
#define PIRQC 11
|
||||
#define PIRQD 12
|
||||
|
||||
/* Map */
|
||||
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
|
||||
|
||||
/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
|
||||
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
|
||||
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
|
||||
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
||||
|
||||
/*
|
||||
* ALIX.2C3 interrupt wiring.
|
||||
*
|
||||
* Devices are:
|
||||
*
|
||||
* 00:01.0 Host bridge: Advanced Micro Devices [AMD] Unknown device 2080 (rev 31)
|
||||
* 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
|
||||
* 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
|
||||
* 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
|
||||
* 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
|
||||
* 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
|
||||
* 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
|
||||
* 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
|
||||
* 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
|
||||
* 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
|
||||
*
|
||||
* The only devices that interrupt are:
|
||||
|
||||
* What Device IRQ PIN PIN WIRED TO
|
||||
* -------------------------------------------------
|
||||
* AES 00:01.2 09 01 A A
|
||||
* eth0 00:09.0 09 01 A B
|
||||
* eth1 00:0a.0 10 01 A C
|
||||
* eth2 00:0b.0 11 01 A D
|
||||
* minipci 00:0c.0 09 01 A A
|
||||
* audio 00:0f.3 05 02 B internal
|
||||
* usb (ohci) 00:0f.4 15 04 D internal
|
||||
* usb (ehci) 00:0f.5 15 04 D internal
|
||||
*
|
||||
*/
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x100B, /* Vendor */
|
||||
0x002B, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0x00, /* Checksum */
|
||||
{
|
||||
/* If you change the number of entries, change IRQ_SLOT_COUNT above! */
|
||||
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
|
||||
/* CPU */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* On-board eth0 */
|
||||
{0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* On-board eth1 */
|
||||
{0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* On-board eth2 */
|
||||
{0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
|
||||
|
||||
/* Mini PCI (slot 1) */
|
||||
{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
|
||||
|
||||
/* Chipset slots */
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
52
mainboard/pcengines/alix2c3/stage1.c
Normal file
52
mainboard/pcengines/alix2c3/stage1.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <lib.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <msr.h>
|
||||
#include <io.h>
|
||||
#include <amd_geodelx.h>
|
||||
#include <southbridge/amd/cs5536/cs5536.h>
|
||||
|
||||
#define SERIAL_IOBASE 0x3f8
|
||||
|
||||
void hardware_stage1(void)
|
||||
{
|
||||
post_code(POST_START_OF_MAIN);
|
||||
geodelx_msr_init();
|
||||
|
||||
cs5536_stage1();
|
||||
|
||||
/* NOTE: must do this AFTER the early_setup!
|
||||
* it is counting on some early MSR setup
|
||||
* for cs5536.
|
||||
*/
|
||||
cs5536_setup_onchipuart(1);
|
||||
}
|
||||
|
||||
void mainboard_pre_payload(void)
|
||||
{
|
||||
geode_pre_payload();
|
||||
banner(BIOS_DEBUG, "mainboard_pre_payload: done");
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue