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190 commits

Author SHA1 Message Date
Unknown W. Brackets
b24f84d1a2 interp: Handle prefixes on matrix init ops. 2019-03-31 17:11:24 -07:00
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59905de719 interp: Correct vsgn out of swizzle bounds. 2019-03-31 17:10:51 -07:00
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b881a689c4 interp: Ignore high bit in vmfvc/vmtvc. 
Both 0 and 128 read/write the S prefix, for example.
 2019-03-31 17:09:55 -07:00
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5749ae09d0 interp: Correct vmfvc register behavior. 
The target and source registers were completely wrong.
 2019-03-31 13:41:48 -07:00
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b2e024025f interp: Handle wrong sizes of vf2h/vh2f. 
Probably not ever used, but they have consistent behavior.
 2019-03-31 13:41:48 -07:00
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af3ed69144 interp: Mask moves to vfpu ctrl. 
These bits of the registers can't be written.
 2019-03-31 10:37:07 -07:00
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d40ac043d4 interp: Handle prefixes for Vmmov/Vmmul/Vmscl. 
I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
 2019-03-31 10:37:07 -07:00
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ec1dae57eb interp: Fix vbfy prefix handling. 2019-03-31 10:09:18 -07:00
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d5273f589a interp: Mask value in vpfxd. 
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
 2019-03-31 08:23:36 -07:00
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7dc775e54f IR: Use interp for unhandled prefix cases. 
The interpreter is not changed yet, so in theory this shouldn't change
behavior.
 2019-03-31 08:17:11 -07:00
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4c3aa841d3 IR: Correct vmmul optimizations. 
It's a bit confusing since it's not D = S*T, but rather D = S'*T.
 2019-03-23 15:31:10 -07:00
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6178a1fb33 Jit: Correct vocp prefix handling. 
See #5549.  Matches tests for various prefix settings.
 2019-02-23 09:15:26 -08:00
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d7f40afd9d interp: Correct vocp prefix handling. 
Also, guess that vsocp also applies prefixes.  See #5549.
 2019-02-21 19:02:16 -08:00
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419c1fbd73 Jit: Respect flags for jit types and features. 
Left some free space for more.
 2019-02-03 14:57:08 -08:00
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46649a218e Core: Add flags to disable jit features. 
Not actually disabling yet, just setup.
 2019-02-03 13:58:24 -08:00
Henrik Rydgård
b4721fbc44 Temporary workaround for another IR interpreter crash. See #10897 2018-04-11 11:55:12 +02:00
Henrik Rydgård
3322adbc22 IR Interpreter: Add some missing instruction metadata. May help part of #10897 2018-04-11 11:16:41 +02:00
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ab809bd19e jit: Apply hasSetRounding at compile time. 
Otherwise, the block will be executed with the wrong rounding mode the
first time rounding is set.  This could be important if it was set for a
single operation.

This is only a problem the first time it's set.
 2018-04-01 10:36:16 -07:00
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09e307b097 arm64jit: Update rounding mode on thread switch. 
Since fcr31 is per-thread, we must update jit state when it changes.
This also fixes the rounding mode on load state and jit/interp switch.
 2018-04-01 10:12:32 -07:00
Henrik Rydgård
34f79904fd IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily. 2018-01-10 09:19:27 +01:00
Henrik Rydgård
fb0e81484b Minor cleanup 2018-01-10 09:19:27 +01:00
Henrik Rydgård
4a32ec3102
Merge pull request #10516 from unknownbrackets/irjit-lwr 
irjit: Optimize out more temps and lwl/lwr operations
 2018-01-10 09:11:10 +01:00
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b6bb0159e3 irjit: Remove Comp_ITypeMemLR. 2018-01-09 18:06:25 -08:00
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f01e06aefd irjit: Improve multiple lwr in a row. 2018-01-07 21:06:02 -08:00
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fbeedd333b irjit: Swap moves when it may allow clobbering. 
Example:
addiu a0, a1, a2
mov s0, a0
addiu a0, a2, a3

By swapping the mov, we can eliminate it.

Only going one back because it's common and didn't want to track reads.
 2018-01-07 21:06:02 -08:00
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d27e428659 irjit: Convert lwr and friends to easier code. 
This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
 2018-01-07 21:06:00 -08:00
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b11f00cead irjit: Combine lwl/lwr and swl/swr, like before. 
Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
 2018-01-07 21:05:58 -08:00
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c6d690e9b8 irjit: Handle Left/Right ops in passes. 2018-01-07 21:05:57 -08:00
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6dda053365 irjit: Add dedicated ops for lwl/swl and friends. 
Temporarily removes optimizations.
 2018-01-07 21:05:57 -08:00
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cd3f4881a5 irjit: Optimize out temp lhs copies. 
Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2

Which was copying s2 before.  This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
 2018-01-07 12:11:16 -08:00
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97674b80bd irjit: Skip preloading blocks with jump to 0. 
These will be changed before executing anyway.
 2018-01-06 17:23:53 -08:00
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cc8e9a93c3 irjit: For debug, return the best block at addr. 
Invalidation may result in multiple matching blocks, prefer any that is
currently valid.
 2018-01-06 17:08:54 -08:00
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463b2a90c7 irjit: Allow precompiling funcs at start. 
This can take a second, but cuts down on jitc spikes throughout runtime.
Note: bits of the game will still be recompiled as games change code.

This is basically the same operation as loading from cache, without the
cache yet.
 2018-01-06 17:06:53 -08:00
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ccd562d934 irjit: Add a safety check for block num overflow. 
In case a game is very frequently modifying some block.
 2018-01-04 23:24:15 -08:00
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0bfab27b46 irjit: Calculate bloat statistics. 
At least based on IR for now.  Can do something else later.

memset() was causing a crash on the std::map.
 2018-01-04 23:09:03 -08:00
Henrik Rydgård
2709472abd
Merge pull request #10506 from hrydgard/ir-interpreter-simd 
More IR interpreter SIMD
 2018-01-05 01:21:32 +01:00
Henrik Rydgård
8c3a50d089
Merge pull request #10505 from hrydgard/ir-disasm-jit-compare 
Show IR disassembly in JIT Compare screen
 2018-01-05 01:20:49 +01:00
Henrik Rydgård
d1d01bfdcb Cleanup GetBlockNumberFromStartAddress 2018-01-05 01:20:10 +01:00
Henrik Rydgård
331a8f91e8 Fix that weird unordered compare mode, hopefully 2018-01-04 20:06:26 +01:00
Henrik Rydgård
18be23eccc IR: More fixes. Still something wrong with VFPU compares (not caused by this PR). 2018-01-04 19:38:36 +01:00
Henrik Rydgård
ca9050b84c On Linux, can't even include nmmintrin without explicitly enabling SSE 4.2 support. 2018-01-04 18:27:19 +01:00
Henrik Rydgård
fe88d12055 IR interpreter: Add some braces to allow variable declaration in the switch cases. 2018-01-04 18:27:19 +01:00
Henrik Rydgård
e0cc126d09 Add some more SIMD support to IR interpreter. Mostly just because, but also serves as implementation reference for later code generation backends. 2018-01-04 18:27:19 +01:00
Henrik Rydgård
a128624f98 IRInterpreter: Fix bugs in floating point truncation functions 2018-01-04 18:25:54 +01:00
Henrik Rydgård
1a97f62dc9 Fix running the CPU test from the UI. 2018-01-04 18:10:41 +01:00
Henrik Rydgård
468b830bec Show IR disassembly in JIT Compare screen 2018-01-04 12:23:23 +01:00
Henrik Rydgård
604b3c3e97 IR Interpreter: Add missing break; to switch case IROp::FSign. 2018-01-04 11:08:56 +01:00
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bc541bd020 irjit: Encode downcount directly as a constant. 
Simpler this way, now.
 2018-01-03 23:32:31 -08:00
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cffb2d61a7 irjit: Embed constant inside IRInst. 
This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
 2018-01-03 23:24:04 -08:00
Unknown W. Brackets
64b57a0329 irjit: Fix swr typo. 
Shifting the wrong direction - oops.
 2018-01-03 08:14:25 -08:00