Unknown W. Brackets
b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit
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riscv: Spill registers more intelligently
2023-07-30 14:49:37 -07:00
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f870271011
riscv: Spill registers more intelligently.
2023-07-30 14:24:12 -07:00
Unknown W. Brackets
f3240393fa
irjit: Use vf for vfpu regs, v0 is a gpr.
2023-07-30 14:16:17 -07:00
Unknown W. Brackets
6819acd29f
irjit: Fix flag on float cond move.
2023-07-30 14:16:17 -07:00
Henrik Rydgård
180bda6f6b
Merge pull request #17799 from unknownbrackets/irjit-lsu
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Add ll/sc to IR and x86jit
2023-07-30 09:15:55 +02:00
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e228748449
irjit: Add FCvtScaledSW to safely scale vi2f.
2023-07-29 18:30:15 -07:00
Unknown W. Brackets
a5a2671af3
irjit: Implement vf2ix.
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Used in LittleBigPlanet when playing intro movies.
2023-07-29 18:01:08 -07:00
Unknown W. Brackets
df2462b1d9
irjit: Implement ll/sc.
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These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
Unknown W. Brackets
df313bd296
riscv: Fix rounding mode setting.
2023-07-25 20:33:56 -07:00
Unknown W. Brackets
9157d992ac
jit-ir: Implement cfc1/ctc1.
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This makes it so we can track rounding mode changes.
2023-07-25 20:33:56 -07:00
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6da10463f9
Debugger: Make reg names safer, stop using v000.
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Better to use S000, etc. as that's more clear throughout.
2023-04-29 09:48:33 -07:00
Unknown W. Brackets
6715f41410
irjit: Add constructs for validing mem access.
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Basically to allow slow/fast memory to work with IR, including for
alignment checks.
2022-08-21 13:01:23 -07:00
Unknown W. Brackets
021f4adfad
irjit: Fix mtv for INF4.
2021-01-09 12:43:50 -08:00
Unknown W. Brackets
670334bd0c
irjit: Correct flags for SetCtrlVFPUReg.
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Fixes #13897 . Caused the reg to be optimized out.
2021-01-09 12:33:08 -08:00
Henrik Rydgård
3322adbc22
IR Interpreter: Add some missing instruction metadata. May help part of #10897
2018-04-11 11:16:41 +02:00
Unknown W. Brackets
6dda053365
irjit: Add dedicated ops for lwl/swl and friends.
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Temporarily removes optimizations.
2018-01-07 21:05:57 -08:00
Unknown W. Brackets
bc541bd020
irjit: Encode downcount directly as a constant.
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Simpler this way, now.
2018-01-03 23:32:31 -08:00
Unknown W. Brackets
cffb2d61a7
irjit: Embed constant inside IRInst.
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This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
2018-01-03 23:24:04 -08:00
Unknown W. Brackets
671be24105
irjit: Add extra temps to make lwl/swl/etc. easier.
2018-01-01 08:38:11 -08:00
Unknown W. Brackets
4578c3cb54
jit-ir: Implement memory breakpoints.
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These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
2016-07-02 16:38:30 -07:00
Unknown W. Brackets
6fb34d0bee
jit-ir: Add initial breakpoint support.
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No memory breakpoints yet, and cache isn't cleared yet so these don't work
exactly the way you might expect...
2016-07-01 17:15:57 -07:00
Henrik Rydgard
f544364c4a
Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm
2016-05-15 23:35:33 +02:00
Henrik Rydgard
d6c2b6e9ae
Most of vi2x
2016-05-15 11:46:01 +02:00
Henrik Rydgard
905af75925
vx2i, vbfy, vsgn
2016-05-15 10:57:43 +02:00
Unknown W. Brackets
4ac773e8b4
jit-ir: Implement bit reverse instruction.
2016-05-14 18:21:42 -07:00
Henrik Rydgard
0541fe36df
Symbian buildfix, fix for fpu test
2016-05-14 15:26:43 +02:00
Henrik Rydgard
64eda6a4ec
IR: Split Syscall into Syscall and ExitToPC, so we can put ApplyRoundingMode in between.
2016-05-14 14:32:22 +02:00
Henrik Rydgard
5b2504120d
Optimize some common prefixes
2016-05-13 20:15:20 +02:00
Unknown W. Brackets
29ed8d2201
jit-ir: ExitToReg doesn't write to registers.
2016-05-12 18:34:27 -07:00
Unknown W. Brackets
d06c6c080c
jit-ir: Expand unused regs to regular GPRs.
2016-05-12 18:30:55 -07:00
Unknown W. Brackets
99468c6fc1
jit-ir: Optimize out unused temp regs.
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This way, if constants have made the temp obsolete (common with ins, for
example), it won't even get set anymore.
2016-05-12 18:30:53 -07:00
Henrik Rydgard
7268abec61
IR: vcmp, vcmov, vhdp
2016-05-12 22:35:31 +02:00
Henrik Rydgard
850d0abc91
IR: More VFPU. Support normal fp compares.
2016-05-12 20:16:15 +02:00
Henrik Rydgard
2cbfb192c4
IR: Lots more VFPU support, some with SIMD
2016-05-12 12:17:25 +02:00
Henrik Rydgard
219548b8e2
Prefix prep
2016-05-11 00:16:07 +02:00
Henrik Rydgard
b3dd36982f
Prefix prep
2016-05-10 23:14:26 +02:00
Henrik Rydgard
db1d1ff9fd
IR: Merge the FPU and VFPU instruction sets, no reason to keep them apart
2016-05-10 22:55:27 +02:00
Henrik Rydgard
45efcda6b1
IR: Some more VFPU
2016-05-10 21:50:08 +02:00
Henrik Rydgard
558bb197c7
More VFPU
2016-05-09 23:47:56 +02:00
Unknown W. Brackets
f6d245f3c4
jit-ir: Remove redundant simplify pass.
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This is just doing the same thing as the const folding pass, really.
2016-05-09 00:13:01 -07:00
Henrik Rydgard
f8659b8e1e
Move the IR interpreter out into its own file. Rename it in the UI. First CMake and Android fixes.
2016-05-08 22:06:13 +02:00
Henrik Rydgard
3eb5480ade
Initial VFPU
2016-05-08 13:32:22 +02:00
Henrik Rydgard
14df39d7c9
Fix IRTEMP clash bug. Add more cases to the constant propagation pass.
2016-05-08 10:36:37 +02:00
Henrik Rydgard
46e839b2b2
ir-jit: Fix bugs in rounding
2016-05-08 02:26:36 +02:00
Henrik Rydgard
7d4774db4c
Fix wsbw
2016-05-08 02:08:25 +02:00
Henrik Rydgard
1a2edc67d0
Add support for float store/load
2016-05-08 02:03:11 +02:00
Henrik Rydgard
ce8aae5ed1
Make the IRJit core selectable in developer tools
2016-05-08 01:43:27 +02:00
Henrik Rydgard
09969c0156
Use the regcache in a new (incomplete) pass, PropagateConstants.
2016-05-08 01:06:07 +02:00
Henrik Rydgard
a33f8b68c6
ir-jit: Get rid of the regcache. Should be replaced with optimization passes.
2016-05-07 23:12:53 +02:00
Henrik Rydgard
750d520cc7
Initial work on mult and friends. Fix another bug.
2016-05-07 22:27:58 +02:00
