mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
589 lines
16 KiB
C++
589 lines
16 KiB
C++
#include "Core/MIPS/IR/IRInst.h"
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#include "Core/MIPS/IR/IRPassSimplify.h"
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#include "Core/MIPS/MIPSDebugInterface.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MemMap.h"
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#include "Core/HLE/HLE.h"
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#include "Core/HLE/ReplaceTables.h"
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#include "math/math_util.h"
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static const IRMeta irMeta[] = {
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{ IROp::SetConst, "SetConst", "GC" },
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{ IROp::Mov, "Mov", "GG" },
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{ IROp::Add, "Add", "GGG" },
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{ IROp::Sub, "Sub", "GGG" },
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{ IROp::Neg, "Neg", "GG" },
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{ IROp::Not, "Not", "GG" },
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{ IROp::And, "And", "GGG" },
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{ IROp::Or, "Or", "GGG" },
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{ IROp::Xor, "Xor", "GGG" },
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{ IROp::AddConst, "AddConst", "GGC" },
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{ IROp::SubConst, "SubConst", "GGC" },
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{ IROp::AndConst, "AndConst", "GGC" },
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{ IROp::OrConst, "OrConst", "GGC" },
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{ IROp::XorConst, "XorConst", "GGC" },
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{ IROp::Shl, "Shl", "GGG" },
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{ IROp::Shr, "Shr", "GGG" },
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{ IROp::Sar, "Sar", "GGG" },
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{ IROp::Ror, "Ror", "GGG" },
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{ IROp::ShlImm, "ShlImm", "GGI" },
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{ IROp::ShrImm, "ShrImm", "GGI" },
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{ IROp::SarImm, "SarImm", "GGI" },
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{ IROp::RorImm, "RorImm", "GGI" },
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{ IROp::Slt, "Slt", "GGG" },
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{ IROp::SltConst, "SltConst", "GGC" },
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{ IROp::SltU, "SltU", "GGG" },
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{ IROp::SltUConst, "SltUConst", "GGC" },
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{ IROp::Clz, "Clz", "GG" },
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{ IROp::MovZ, "MovZ", "GGG" },
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{ IROp::MovNZ, "MovNZ", "GGG" },
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{ IROp::Max, "Max", "GGG" },
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{ IROp::Min, "Min", "GGG" },
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{ IROp::BSwap16, "BSwap16", "GG" },
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{ IROp::BSwap32, "BSwap32", "GG" },
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{ IROp::Mult, "Mult", "_GG" },
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{ IROp::MultU, "MultU", "_GG" },
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{ IROp::Madd, "Madd", "_GG" },
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{ IROp::MaddU, "MaddU", "_GG" },
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{ IROp::Msub, "Msub", "_GG" },
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{ IROp::MsubU, "MsubU", "_GG" },
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{ IROp::Div, "Div", "_GG" },
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{ IROp::DivU, "DivU", "_GG" },
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{ IROp::MtLo, "MtLo", "_G" },
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{ IROp::MtHi, "MtHi", "_G" },
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{ IROp::MfLo, "MfLo", "G" },
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{ IROp::MfHi, "MfHi", "G" },
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{ IROp::Ext8to32, "Ext8to32", "GG" },
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{ IROp::Ext16to32, "Ext16to32", "GG" },
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{ IROp::Load8, "Load8", "GGC" },
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{ IROp::Load8Ext, "Load8", "GGC" },
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{ IROp::Load16, "Load16", "GGC" },
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{ IROp::Load16Ext, "Load16Ext", "GGC" },
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{ IROp::Load32, "Load32", "GGC" },
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{ IROp::LoadFloat, "LoadFloat", "FGC" },
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{ IROp::Store8, "Store8", "GGC" },
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{ IROp::Store16, "Store16", "GGC" },
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{ IROp::Store32, "Store32", "GGC" },
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{ IROp::StoreFloat, "StoreFloat", "FGC" },
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{ IROp::FAdd, "FAdd", "FFF" },
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{ IROp::FSub, "FSub", "FFF" },
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{ IROp::FMul, "FMul", "FFF" },
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{ IROp::FDiv, "FDiv", "FFF" },
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{ IROp::FMov, "FMov", "FF" },
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{ IROp::FSqrt, "FSqrt", "FF" },
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{ IROp::FNeg, "FNeg", "FF" },
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{ IROp::FAbs, "FAbs", "FF" },
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{ IROp::FRound, "FRound", "FF" },
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{ IROp::FTrunc, "FTrunc", "FF" },
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{ IROp::FCeil, "FCeil", "FF" },
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{ IROp::FFloor, "FFloor", "FF" },
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{ IROp::FCvtWS, "FCvtWS", "FF" },
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{ IROp::FCvtSW, "FCvtSW", "FF" },
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{ IROp::FMovFromGPR, "FMovFromGPR", "FG" },
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{ IROp::FMovToGPR, "FMovToGPR", "GF" },
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{ IROp::FpCondToReg, "FpCondToReg", "G" },
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{ IROp::VfpuCtrlToReg, "VfpuCtrlToReg", "GI" },
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{ IROp::SetCtrlVFPU, "SetCtrlVFPU", "TC" },
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{ IROp::Interpret, "Interpret", "_C" },
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{ IROp::Downcount, "Downcount", "_II" },
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{ IROp::ExitToConst, "Exit", "C" },
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{ IROp::ExitToConstIfEq, "ExitIfEq", "CGG" },
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{ IROp::ExitToConstIfNeq, "ExitIfNeq", "CGG" },
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{ IROp::ExitToConstIfGtZ, "ExitIfGtZ", "CG" },
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{ IROp::ExitToConstIfGeZ, "ExitIfGeZ", "CG" },
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{ IROp::ExitToConstIfLeZ, "ExitIfLeZ", "CG" },
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{ IROp::ExitToConstIfLtZ, "ExitIfLtZ", "CG" },
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{ IROp::ExitToReg, "ExitToReg", "G" },
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{ IROp::Syscall, "Syscall", "_C" },
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{ IROp::Break, "Break", ""},
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{ IROp::SetPC, "SetPC", "_G" },
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{ IROp::SetPCConst, "SetPC", "_C" },
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{ IROp::CallReplacement, "CallRepl", "_C"},
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};
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const IRMeta *metaIndex[256];
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void InitIR() {
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for (size_t i = 0; i < ARRAY_SIZE(irMeta); i++) {
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metaIndex[(int)irMeta[i].op] = &irMeta[i];
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}
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}
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u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int count) {
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const IRInst *end = inst + count;
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while (inst != end) {
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switch (inst->op) {
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case IROp::SetConst:
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mips->r[inst->dest] = constPool[inst->src1];
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break;
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case IROp::Add:
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mips->r[inst->dest] = mips->r[inst->src1] + mips->r[inst->src2];
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break;
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case IROp::Sub:
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mips->r[inst->dest] = mips->r[inst->src1] - mips->r[inst->src2];
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break;
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case IROp::And:
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mips->r[inst->dest] = mips->r[inst->src1] & mips->r[inst->src2];
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break;
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case IROp::Or:
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mips->r[inst->dest] = mips->r[inst->src1] | mips->r[inst->src2];
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break;
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case IROp::Xor:
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mips->r[inst->dest] = mips->r[inst->src1] ^ mips->r[inst->src2];
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break;
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case IROp::Mov:
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mips->r[inst->dest] = mips->r[inst->src1];
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break;
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case IROp::AddConst:
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mips->r[inst->dest] = mips->r[inst->src1] + constPool[inst->src2];
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break;
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case IROp::SubConst:
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mips->r[inst->dest] = mips->r[inst->src1] - constPool[inst->src2];
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break;
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case IROp::AndConst:
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mips->r[inst->dest] = mips->r[inst->src1] & constPool[inst->src2];
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break;
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case IROp::OrConst:
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mips->r[inst->dest] = mips->r[inst->src1] | constPool[inst->src2];
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break;
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case IROp::XorConst:
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mips->r[inst->dest] = mips->r[inst->src1] ^ constPool[inst->src2];
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break;
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case IROp::Neg:
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mips->r[inst->dest] = -(s32)mips->r[inst->src1];
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break;
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case IROp::Not:
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mips->r[inst->dest] = ~mips->r[inst->src1];
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break;
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case IROp::Ext8to32:
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mips->r[inst->dest] = (s32)(s8)mips->r[inst->src1];
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break;
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case IROp::Ext16to32:
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mips->r[inst->dest] = (s32)(s16)mips->r[inst->src1];
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break;
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case IROp::Load8:
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mips->r[inst->dest] = Memory::ReadUnchecked_U8(mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::Load8Ext:
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mips->r[inst->dest] = (s32)(s8)Memory::ReadUnchecked_U8(mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::Load16:
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mips->r[inst->dest] = Memory::ReadUnchecked_U16(mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::Load16Ext:
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mips->r[inst->dest] = (s32)(s16)Memory::ReadUnchecked_U16(mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::Load32:
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mips->r[inst->dest] = Memory::ReadUnchecked_U32(mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::LoadFloat:
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mips->f[inst->dest] = Memory::ReadUnchecked_Float(mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::Store8:
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Memory::WriteUnchecked_U8(mips->r[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::Store16:
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Memory::WriteUnchecked_U16(mips->r[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::Store32:
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Memory::WriteUnchecked_U32(mips->r[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::StoreFloat:
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Memory::WriteUnchecked_Float(mips->f[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::ShlImm:
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mips->r[inst->dest] = mips->r[inst->src1] << (int)inst->src2;
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break;
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case IROp::ShrImm:
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mips->r[inst->dest] = mips->r[inst->src1] >> (int)inst->src2;
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break;
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case IROp::SarImm:
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mips->r[inst->dest] = (s32)mips->r[inst->src1] >> (int)inst->src2;
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break;
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case IROp::RorImm:
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{
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u32 x = mips->r[inst->src1];
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int sa = inst->src2;
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mips->r[inst->dest] = (x >> sa) | (x << (32 - sa));
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}
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break;
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case IROp::Shl:
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mips->r[inst->dest] = mips->r[inst->src1] << (mips->r[inst->src2] & 31);
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break;
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case IROp::Shr:
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mips->r[inst->dest] = mips->r[inst->src1] >> (mips->r[inst->src2] & 31);
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break;
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case IROp::Sar:
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mips->r[inst->dest] = (s32)mips->r[inst->src1] >> (mips->r[inst->src2] & 31);
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break;
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case IROp::Ror:
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{
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u32 x = mips->r[inst->src1];
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int sa = mips->r[inst->src2] & 31;
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mips->r[inst->dest] = (x >> sa) | (x << (32 - sa));
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}
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break;
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case IROp::Clz:
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{
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int x = 31;
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int count = 0;
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int value = mips->r[inst->src1];
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while (x >= 0 && !(value & (1 << x))) {
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count++;
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x--;
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}
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mips->r[inst->dest] = count;
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break;
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}
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case IROp::Slt:
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mips->r[inst->dest] = (s32)mips->r[inst->src1] < (s32)mips->r[inst->src2];
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break;
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case IROp::SltU:
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mips->r[inst->dest] = mips->r[inst->src1] < mips->r[inst->src2];
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break;
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case IROp::SltConst:
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mips->r[inst->dest] = (s32)mips->r[inst->src1] < (s32)constPool[inst->src2];
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break;
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case IROp::SltUConst:
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mips->r[inst->dest] = mips->r[inst->src1] < constPool[inst->src2];
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break;
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case IROp::MovZ:
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if (mips->r[inst->src1] == 0)
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mips->r[inst->dest] = mips->r[inst->src2];
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break;
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case IROp::MovNZ:
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if (mips->r[inst->src1] != 0)
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mips->r[inst->dest] = mips->r[inst->src2];
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break;
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case IROp::Max:
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mips->r[inst->dest] = (s32)mips->r[inst->src1] > (s32)mips->r[inst->src2] ? mips->r[inst->src1] : mips->r[inst->src2];
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break;
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case IROp::Min:
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mips->r[inst->dest] = (s32)mips->r[inst->src1] < (s32)mips->r[inst->src2] ? mips->r[inst->src1] : mips->r[inst->src2];
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break;
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case IROp::MtLo:
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mips->lo = mips->r[inst->src1];
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break;
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case IROp::MtHi:
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mips->hi = mips->r[inst->src1];
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break;
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case IROp::MfLo:
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mips->r[inst->dest] = mips->lo;
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break;
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case IROp::MfHi:
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mips->r[inst->dest] = mips->hi;
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break;
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case IROp::Mult:
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{
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s64 result = (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
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memcpy(&mips->lo, &result, 8);
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break;
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}
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case IROp::MultU:
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{
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u64 result = (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
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memcpy(&mips->lo, &result, 8);
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break;
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}
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case IROp::BSwap16:
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{
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u32 x = mips->r[inst->src1];
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mips->r[inst->dest] = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8);
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break;
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}
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case IROp::BSwap32:
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{
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u32 x = mips->r[inst->src1];
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mips->r[inst->dest] = ((x & 0xFF000000) >> 24) | ((x & 0x00FF0000) >> 8) | ((x & 0x0000FF00) << 8) | ((x & 0x000000FF) << 24);
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break;
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}
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case IROp::FAdd:
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mips->f[inst->dest] = mips->f[inst->src1] + mips->f[inst->src2];
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break;
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case IROp::FSub:
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mips->f[inst->dest] = mips->f[inst->src1] - mips->f[inst->src2];
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break;
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case IROp::FMul:
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mips->f[inst->dest] = mips->f[inst->src1] * mips->f[inst->src2];
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break;
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case IROp::FDiv:
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mips->f[inst->dest] = mips->f[inst->src1] / mips->f[inst->src2];
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break;
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case IROp::FMov:
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mips->f[inst->dest] = mips->f[inst->src1];
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break;
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case IROp::FAbs:
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mips->f[inst->dest] = fabsf(mips->f[inst->src1]);
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break;
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case IROp::FSqrt:
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mips->f[inst->dest] = sqrtf(mips->f[inst->src1]);
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break;
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case IROp::FNeg:
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mips->f[inst->dest] = -mips->f[inst->src1];
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break;
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case IROp::FpCondToReg:
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mips->r[inst->dest] = mips->fpcond;
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break;
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case IROp::VfpuCtrlToReg:
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mips->r[inst->dest] = mips->vfpuCtrl[inst->src1];
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break;
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case IROp::FRound:
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mips->fs[inst->dest] = (int)floorf(mips->f[inst->src1] + 0.5f);
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break;
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case IROp::FTrunc:
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{
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float src = mips->f[inst->src1];
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if (src >= 0.0f) {
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mips->fs[inst->dest] = (int)floorf(src);
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// Overflow, but it was positive.
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if (mips->fs[inst->dest] == -2147483648LL) {
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mips->fs[inst->dest] = 2147483647LL;
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}
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} else {
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// Overflow happens to be the right value anyway.
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mips->fs[inst->dest] = (int)ceilf(src);
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}
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break;
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}
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case IROp::FCeil:
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mips->fs[inst->dest] = (int)ceilf(mips->f[inst->src1]);
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break;
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case IROp::FFloor:
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mips->fs[inst->dest] = (int)floorf(mips->f[inst->src1]);
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break;
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case IROp::FCvtSW:
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mips->f[inst->dest] = (float)mips->fs[inst->src1];
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break;
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case IROp::FCvtWS:
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{
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float src = mips->f[inst->src1];
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if (my_isnanorinf(src))
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{
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mips->fs[inst->dest] = my_isinf(src) && src < 0.0f ? -2147483648LL : 2147483647LL;
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break;
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}
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switch (mips->fcr31 & 3)
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{
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case 0: mips->fs[inst->dest] = (int)round_ieee_754(src); break; // RINT_0
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case 1: mips->fs[inst->dest] = (int)src; break; // CAST_1
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case 2: mips->fs[inst->dest] = (int)ceilf(src); break; // CEIL_2
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case 3: mips->fs[inst->dest] = (int)floorf(src); break; // FLOOR_3
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}
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break; //cvt.w.s
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}
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case IROp::ZeroFpCond:
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mips->fpcond = 0;
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break;
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case IROp::FMovFromGPR:
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memcpy(&mips->f[inst->dest], &mips->r[inst->src1], 4);
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break;
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case IROp::FMovToGPR:
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memcpy(&mips->r[inst->dest], &mips->f[inst->src1], 4);
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break;
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case IROp::ExitToConst:
|
|
return constPool[inst->dest];
|
|
|
|
case IROp::ExitToReg:
|
|
return mips->r[inst->dest];
|
|
|
|
case IROp::ExitToConstIfEq:
|
|
if (mips->r[inst->src1] == mips->r[inst->src2])
|
|
return constPool[inst->dest];
|
|
break;
|
|
case IROp::ExitToConstIfNeq:
|
|
if (mips->r[inst->src1] != mips->r[inst->src2])
|
|
return constPool[inst->dest];
|
|
break;
|
|
case IROp::ExitToConstIfGtZ:
|
|
if ((s32)mips->r[inst->src1] > 0)
|
|
return constPool[inst->dest];
|
|
break;
|
|
case IROp::ExitToConstIfGeZ:
|
|
if ((s32)mips->r[inst->src1] >= 0)
|
|
return constPool[inst->dest];
|
|
break;
|
|
case IROp::ExitToConstIfLtZ:
|
|
if ((s32)mips->r[inst->src1] < 0)
|
|
return constPool[inst->dest];
|
|
break;
|
|
case IROp::ExitToConstIfLeZ:
|
|
if ((s32)mips->r[inst->src1] <= 0)
|
|
return constPool[inst->dest];
|
|
break;
|
|
|
|
case IROp::Downcount:
|
|
mips->downcount -= (inst->src1) | ((inst->src2) << 8);
|
|
break;
|
|
|
|
case IROp::SetPC:
|
|
mips->pc = mips->r[inst->src1];
|
|
break;
|
|
|
|
case IROp::SetPCConst:
|
|
mips->pc = constPool[inst->src1];
|
|
break;
|
|
|
|
case IROp::Syscall:
|
|
// SetPC was executed before.
|
|
{
|
|
MIPSOpcode op(constPool[inst->src1]);
|
|
CallSyscall(op);
|
|
return mips->pc;
|
|
}
|
|
|
|
case IROp::Interpret: // SLOW fallback. Can be made faster.
|
|
{
|
|
MIPSOpcode op(constPool[inst->src1]);
|
|
MIPSInterpret(op);
|
|
break;
|
|
}
|
|
|
|
case IROp::CallReplacement:
|
|
{
|
|
int funcIndex = constPool[inst->src1];
|
|
const ReplacementTableEntry *f = GetReplacementFunc(funcIndex);
|
|
int cycles = f->replaceFunc();
|
|
mips->downcount -= cycles;
|
|
return mips->r[MIPS_REG_RA];
|
|
}
|
|
|
|
case IROp::Break:
|
|
Crash();
|
|
break;
|
|
|
|
case IROp::SetCtrlVFPU:
|
|
mips->vfpuCtrl[inst->dest] = constPool[inst->src1];
|
|
break;
|
|
|
|
default:
|
|
Crash();
|
|
}
|
|
#ifdef _DEBUG
|
|
if (mips->r[0] != 0)
|
|
Crash();
|
|
#endif
|
|
inst++;
|
|
}
|
|
|
|
// If we got here, the block was badly constructed.
|
|
Crash();
|
|
return 0;
|
|
}
|
|
|
|
void IRWriter::Write(IROp op, u8 dst, u8 src1, u8 src2) {
|
|
IRInst inst;
|
|
inst.op = op;
|
|
inst.dest = dst;
|
|
inst.src1 = src1;
|
|
inst.src2 = src2;
|
|
insts_.push_back(inst);
|
|
}
|
|
|
|
void IRWriter::WriteSetConstant(u8 dst, u32 value) {
|
|
Write(IROp::SetConst, dst, AddConstant(value));
|
|
}
|
|
|
|
int IRWriter::AddConstant(u32 value) {
|
|
for (size_t i = 0; i < constPool_.size(); i++) {
|
|
if (constPool_[i] == value)
|
|
return (int)i;
|
|
}
|
|
constPool_.push_back(value);
|
|
if (constPool_.size() > 255) {
|
|
// Cannot have more than 256 constants in a block!
|
|
Crash();
|
|
}
|
|
return (int)constPool_.size() - 1;
|
|
}
|
|
|
|
int IRWriter::AddConstantFloat(float value) {
|
|
u32 val;
|
|
memcpy(&val, &value, 4);
|
|
return AddConstant(val);
|
|
}
|
|
|
|
void IRWriter::Simplify() {
|
|
SimplifyInPlace(&insts_[0], (int)insts_.size(), constPool_.data());
|
|
}
|
|
|
|
const char *GetGPRName(int r) {
|
|
if (r < 32) {
|
|
return currentDebugMIPS->GetRegName(0, r);
|
|
}
|
|
switch (r) {
|
|
case IRTEMP_0: return "irtemp0";
|
|
case IRTEMP_1: return "irtemp1";
|
|
case IRTEMP_LHS: return "irtemp_lhs";
|
|
case IRTEMP_RHS: return "irtemp_rhs";
|
|
default: return "(unk)";
|
|
}
|
|
}
|
|
|
|
void DisassembleParam(char *buf, int bufSize, u8 param, char type, const u32 *constPool) {
|
|
switch (type) {
|
|
case 'G':
|
|
snprintf(buf, bufSize, "%s", GetGPRName(param));
|
|
break;
|
|
case 'F':
|
|
snprintf(buf, bufSize, "r%d", param);
|
|
break;
|
|
case 'C':
|
|
snprintf(buf, bufSize, "%08x", constPool[param]);
|
|
break;
|
|
case 'I':
|
|
snprintf(buf, bufSize, "%02x", param);
|
|
break;
|
|
case '_':
|
|
case '\0':
|
|
buf[0] = 0;
|
|
break;
|
|
default:
|
|
snprintf(buf, bufSize, "?");
|
|
break;
|
|
}
|
|
}
|
|
|
|
const IRMeta *GetIRMeta(IROp op) {
|
|
return metaIndex[(int)op];
|
|
}
|
|
|
|
void DisassembleIR(char *buf, size_t bufsize, IRInst inst, const u32 *constPool) {
|
|
const IRMeta *meta = GetIRMeta(inst.op);
|
|
if (!meta) {
|
|
snprintf(buf, bufsize, "Unknown %d", (int)inst.op);
|
|
return;
|
|
}
|
|
char bufDst[16];
|
|
char bufSrc1[16];
|
|
char bufSrc2[16];
|
|
DisassembleParam(bufDst, sizeof(bufDst) - 2, inst.dest, meta->types[0], constPool);
|
|
DisassembleParam(bufSrc1, sizeof(bufSrc1) - 2, inst.src1, meta->types[1], constPool);
|
|
DisassembleParam(bufSrc2, sizeof(bufSrc2), inst.src2, meta->types[2], constPool);
|
|
if (meta->types[1] && meta->types[0] != '_') {
|
|
strcat(bufDst, ", ");
|
|
}
|
|
if (meta->types[2] && meta->types[1] != '_') {
|
|
strcat(bufSrc1, ", ");
|
|
}
|
|
snprintf(buf, bufsize, "%s %s%s%s", meta->name, bufDst, bufSrc1, bufSrc2);
|
|
}
|