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https://github.com/hrydgard/ppsspp.git
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Initial VFPU
This commit is contained in:
Henrik Rydgard
parent
98113edbd4
commit
3eb5480ade
3 changed files with 122 additions and 4 deletions
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@ -181,7 +181,38 @@ namespace MIPSComp {
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}
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void IRJit::Comp_SVQ(MIPSOpcode op) {
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DISABLE;
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int imm = (signed short)(op & 0xFFFC);
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int vt = (((op >> 16) & 0x1f)) | ((op & 1) << 5);
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MIPSGPReg rs = _RS;
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u8 vregs[4];
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GetVectorRegs(vregs, V_Quad, vt);
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switch (op >> 26) {
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case 54: //lv.q
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{
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// TODO: Add vector load/store instruction to the IR
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ir.Write(IROp::LoadFloatV, vregs[0], rs, ir.AddConstant(imm));
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ir.Write(IROp::LoadFloatV, vregs[1], rs, ir.AddConstant(imm + 4));
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ir.Write(IROp::LoadFloatV, vregs[2], rs, ir.AddConstant(imm + 8));
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ir.Write(IROp::LoadFloatV, vregs[3], rs, ir.AddConstant(imm + 12));
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}
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break;
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case 62: //sv.q
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{
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// CC might be set by slow path below, so load regs first.
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ir.Write(IROp::StoreFloatV, vregs[0], rs, ir.AddConstant(imm));
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ir.Write(IROp::StoreFloatV, vregs[1], rs, ir.AddConstant(imm + 4));
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ir.Write(IROp::StoreFloatV, vregs[2], rs, ir.AddConstant(imm + 8));
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ir.Write(IROp::StoreFloatV, vregs[3], rs, ir.AddConstant(imm + 12));
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}
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break;
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default:
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DISABLE;
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break;
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}
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}
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void IRJit::Comp_VVectorInit(MIPSOpcode op) {
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@ -215,6 +246,11 @@ namespace MIPSComp {
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}
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void IRJit::Comp_VV2Op(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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// Pre-processing: Eliminate silly no-op VMOVs, common in Wipeout Pure
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if (((op >> 16) & 0x1f) == 0 && _VS == _VD && js.HasNoPrefix()) {
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return;
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}
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DISABLE;
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}
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@ -231,7 +267,33 @@ namespace MIPSComp {
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}
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void IRJit::Comp_Mftv(MIPSOpcode op) {
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DISABLE;
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int imm = op & 0xFF;
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MIPSGPReg rt = _RT;
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switch ((op >> 21) & 0x1f) {
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case 3: //mfv / mfvc
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// rt = 0, imm = 255 appears to be used as a CPU interlock by some games.
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if (rt != 0) {
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if (imm < 128) { //R(rt) = VI(imm);
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ir.Write(IROp::VMovToGPR, rt, imm);
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logBlocks = 1;
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} else {
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DISABLE;
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}
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}
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break;
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case 7: // mtv
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if (imm < 128) {
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ir.Write(IROp::VMovFromGPR, imm, rt);
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logBlocks = 1;
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} else {
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DISABLE;
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}
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break;
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default:
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DISABLE;
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}
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}
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void IRJit::Comp_Vmfvc(MIPSOpcode op) {
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@ -10,6 +10,8 @@
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static const IRMeta irMeta[] = {
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{ IROp::SetConst, "SetConst", "GC" },
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{ IROp::SetConstF, "SetConstF", "FC" },
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{ IROp::SetConstV, "SetConstV", "VC" },
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{ IROp::Mov, "Mov", "GG" },
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{ IROp::Add, "Add", "GGG" },
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{ IROp::Sub, "Sub", "GGG" },
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@ -62,10 +64,12 @@ static const IRMeta irMeta[] = {
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{ IROp::Load16Ext, "Load16Ext", "GGC" },
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{ IROp::Load32, "Load32", "GGC" },
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{ IROp::LoadFloat, "LoadFloat", "FGC" },
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{ IROp::LoadFloatV, "LoadFloatV", "VGC" },
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{ IROp::Store8, "Store8", "GGC" },
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{ IROp::Store16, "Store16", "GGC" },
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{ IROp::Store32, "Store32", "GGC" },
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{ IROp::StoreFloat, "StoreFloat", "FGC" },
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{ IROp::StoreFloatV, "StoreFloatV", "VGC" },
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{ IROp::FAdd, "FAdd", "FFF" },
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{ IROp::FSub, "FSub", "FFF" },
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{ IROp::FMul, "FMul", "FFF" },
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@ -82,6 +86,8 @@ static const IRMeta irMeta[] = {
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{ IROp::FCvtSW, "FCvtSW", "FF" },
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{ IROp::FMovFromGPR, "FMovFromGPR", "FG" },
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{ IROp::FMovToGPR, "FMovToGPR", "GF" },
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{ IROp::VMovFromGPR, "VMovFromGPR", "VG" },
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{ IROp::VMovToGPR, "VMovToGPR", "GV" },
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{ IROp::FpCondToReg, "FpCondToReg", "G" },
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{ IROp::VfpuCtrlToReg, "VfpuCtrlToReg", "GI" },
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{ IROp::SetCtrlVFPU, "SetCtrlVFPU", "TC" },
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@ -117,6 +123,12 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
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case IROp::SetConst:
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mips->r[inst->dest] = constPool[inst->src1];
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break;
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case IROp::SetConstF:
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memcpy(&mips->f[inst->dest], &constPool[inst->src1], 4);
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break;
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case IROp::SetConstV:
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memcpy(&mips->f[inst->dest], &constPool[inst->src1], 4);
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break;
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case IROp::Add:
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mips->r[inst->dest] = mips->r[inst->src1] + mips->r[inst->src2];
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break;
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@ -181,6 +193,9 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
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case IROp::LoadFloat:
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mips->f[inst->dest] = Memory::ReadUnchecked_Float(mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::LoadFloatV:
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mips->v[voffset[inst->dest]] = Memory::ReadUnchecked_Float(mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::Store8:
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Memory::WriteUnchecked_U8(mips->r[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
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@ -194,6 +209,9 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
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case IROp::StoreFloat:
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Memory::WriteUnchecked_Float(mips->f[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::StoreFloatV:
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Memory::WriteUnchecked_Float(mips->v[voffset[inst->src3]], mips->r[inst->src1] + constPool[inst->src2]);
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break;
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case IROp::ShlImm:
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mips->r[inst->dest] = mips->r[inst->src1] << (int)inst->src2;
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@ -389,6 +407,7 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
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}
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break; //cvt.w.s
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}
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case IROp::ZeroFpCond:
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mips->fpcond = 0;
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break;
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@ -400,6 +419,13 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
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memcpy(&mips->r[inst->dest], &mips->f[inst->src1], 4);
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break;
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case IROp::VMovFromGPR:
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memcpy(&mips->v[voffset[inst->dest]], &mips->r[inst->src1], 4);
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break;
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case IROp::VMovToGPR:
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memcpy(&mips->r[inst->dest], &mips->v[voffset[inst->src1]], 4);
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break;
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case IROp::ExitToConst:
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return constPool[inst->dest];
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@ -540,12 +566,31 @@ const char *GetGPRName(int r) {
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}
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void DisassembleParam(char *buf, int bufSize, u8 param, char type, const u32 *constPool) {
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static const char *vfpuCtrlNames[VFPU_CTRL_MAX] = {
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"SPFX",
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"TPFX",
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"DPFX",
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"CC",
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"INF4",
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"RSV5",
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"RSV6",
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"REV",
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"RCX0",
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"RCX1",
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"RCX2",
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"RCX3",
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"RCX4",
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"RCX5",
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"RCX6",
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"RCX7",
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};
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switch (type) {
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case 'G':
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snprintf(buf, bufSize, "%s", GetGPRName(param));
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break;
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case 'F':
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snprintf(buf, bufSize, "r%d", param);
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snprintf(buf, bufSize, "f%d", param);
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break;
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case 'C':
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snprintf(buf, bufSize, "%08x", constPool[param]);
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@ -553,6 +598,12 @@ void DisassembleParam(char *buf, int bufSize, u8 param, char type, const u32 *co
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case 'I':
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snprintf(buf, bufSize, "%02x", param);
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break;
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case 'V':
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snprintf(buf, bufSize, "v%d", param);
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break;
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case 'T':
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snprintf(buf, bufSize, "%s", vfpuCtrlNames[param]);
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break;
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case '_':
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case '\0':
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buf[0] = 0;
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@ -17,7 +17,8 @@
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enum class IROp : u8 {
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SetConst,
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FSetConst,
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SetConstF,
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SetConstV,
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Mov,
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@ -88,11 +89,13 @@ enum class IROp : u8 {
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Load16Ext,
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Load32,
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LoadFloat,
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LoadFloatV,
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Store8,
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Store16,
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Store32,
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StoreFloat,
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StoreFloatV,
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Ext8to32,
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Ext16to32,
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@ -136,6 +139,8 @@ enum class IROp : u8 {
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UpdateRoundingMode,
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SetCtrlVFPU,
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VMovFromGPR,
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VMovToGPR,
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// Fake/System instructions
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Interpret,
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